Synopsys Addresses Multi-Standard Verification of Chips With Flexible Telecom Workbench

Product Addition to Verification Intellectual Property (IP) Portfolio Adds Support for Next Generation SONET/SDH Systems-on-Chips

MOUNTAIN VIEW, Calif., December 18, 2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, today introduced Telecom Workbench, a new product that addresses functional and conformance verification of multi-standard systems-on-chips (SoCs). Telecom Workbench combines support for multiple broadband protocols such as Internet protocol (IP) and ATM, with support for the next generation of SONET/SDH standards by adding features that address virtual concatenation, LCAS, and GFP. By integrating conformance testing within the functional verification environment early in the design cycle, Telecom Workbench provides designers of modern networking chips with powerful diagnostic capabilities for validating standards interoperability that are traditionally available in the lab only after silicon has been produced.

"Increasingly, a single chip is being used to handle a number of different standards for transporting multiple protocols over metropolitan, storage and wide area networks," said Joachim Kunkel, vice president of marketing, Synopsys IP and Design Services. "Telecom Workbench is unique in its comprehensive support for verifying the conformance of these complex chips to industry standards, thereby reducing the risk of finding catastrophic bugs late in the design cycle. Chip developers save time and costs by addressing functional and conformance verification with this single product."

Acterna, the world's largest provider of test solutions for optical transport, access and cable networks, has adopted Synopsys' Telecom Workbench as part of its verification environment and has successfully used it for the conformance testing of chips they have recently taped out.

"Synopsys' Telecom Workbench provides a second pair of eyes to check conformance with industry standards before a chip gets to silicon and is tested in the lab," said Guido Frangenberg, vice president, product marketing, Transport Division at Acterna. "It creates a flexible verification environment that generates and analyzes protocols and signals for all layers and standards involved in optical transport test equipment. By enabling easy handling of complex telecom structures such as frames, cells and packets, the workbench increases the designer's capability and confidence in the verification coverage of the design, and enables a more predictable design cycle in terms of cost and time."

Telecom Workbench is a collection of parameterizable and programmable models used to automate the generation and analysis of signals needed for testing standards conformance at different levels of the design (i.e., system specification, algorithm design, implementation and system integration). A single license of Telecom Workbench directly supports designs based on the following standards:

• ATM: Asynchronous Transfer Mode
• GFP: Generic Framing Procedure
• IP: Internet Protocol
• LAPS: Link Access Procedure SDH
• PDH: Plesiochronous Digital Hierarchy
• POS-PHY: Packet Over Sonet-PHYsical Interface
• PPP: Point-to-Point Protocol
• SDH: Synchronous Digital Hierarchy
• SONET: Synchronous Optical NETwork
• SPI-4: System Packet Interface Level 4
• UTOPIA: Universal Test and Operations Physical Interface for ATM

Telecom Workbench expands Synopsys' portfolio of verification IP, and leverages the more than ten years of experience of Synopsys Professional Services' broadband product group in telecommunications design and conformance verification. Telecom Workbench includes support for CoCentric® System Studio for transaction-based architecture design as well as VCS™ and Vera® for register-transfer level (RTL) verification.

Pricing and Availability
Telecom Workbench is currently available to customers for US $14,700 for a one-year technology subscription license (TSL).

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Synopsys, CoCentric and Vera are registered trademarks, and VCS is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.