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Xilinx Delivers New Adaptive I/O Solution to Reduce Serial Design Cost and Improve Time to MarketInnovative solution demonstrates benefits of combining the PowerPC processor and 3.125Gbps serial transceivers only available in the Virtex-II Pro Platform FPGA SAN JOSE, Calif., January 15, 2003 - Xilinx, Inc., (NASDAQ:XLNX) today announced the availability of a new adaptive I/O solution, enabling system designers to automate the process of fine tuning serial I/O to achieve maximum system performance. The solution includes three new reference designs, addressing applications such as communication line cards where the highest level of interoperability among various suppliers' chips is critical to the overall cost, development time and performance of systems. Part of the Xilinx Serial Tsunami initiative, the solution helps designers easily migrate to serial technology and will be discussed at the upcoming Platform Conference held at the Silicon Valley Conference Center in San Jose, CA on January 28th and 29th, 2003. "Leveraging the embedded PowerPC™ processor and 3.125Gbps serial transceiver embedded into the Virtex-II Pro™ Platform FPGA, this innovative solution now allows designers to optimize system performance and reduce design cycles in both the diagnostic and deployment phases of system design," said Andy DeBaets, senior director of applications and systems engineering at Xilinx. "Not only does this solution reduce the overall cost of system design, but it also improves customers' time to market." The reference designs underscore Xilinx's commitment to support the broad industry trend toward serial connectivity - dubbed it's Serial Tsunami initiative - which is being driven by companies across a wide range of industries as a means to reduce system costs, simplify system design, and provide scalability to meet new bandwidth requirements. Adaptive I/O in diagnostic phase Bit error rate tester Adaptive I/O in mission mode Availability About Xilinx
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