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SiWorks Inc. Launches High Speed FFT and Viterbi Cores(Calgary, Canada - Feb. 6, 2003) - SiWorks Inc. a leading provider of semiconductor design services and semiconductor intellectual property, today announced that it has released a high throughput parallel FFT core and a high throughput Viterbi core. The company now offers an extensive portfolio of signal processing cores for wired and wireless communication applications. "Our customers are demanding higher speed versions of our existing cores for both FPGA prototyping and ASIC implementations," says Roger Bertschmann, President of SiWorks. "Market acceptance of our existing FFT and Viterbi cores into the WLAN 802.11 and other markets has been extremely high and we are now seeing increasing demands from customers looking at new applications and pushing transmission speeds and data rates beyond the rates initially contemplated by the standards. As a result, we have developed new high-speed versions of our FFT and Viterbi cores." A brief summary of the performance benefits achieved by the cores is provided below. High Speed Parallel FFT/IFFT Core: SiWorks has completed the development of an FFT/IFFT generator which has the ability to produce N-point FFT/IFFT HDL code with 1 to P (P<=N) samples being computed in parallel. FFT cores can be produced which take 1, 2, 4, 8, .., P samples in parallel. The resulting FFT cores are capable of extremely high data throughput. Applications include broadband networking and highspeed wireless data reception. A benchmark is provided below:
This implementation processes four samples in parallel, runs at a 100 MHz clock rate and processes a complete1024-pt FFT in 2.5 us. The maximum clock speed was limited by the FPGA. ASIC speeds of greater than 200 MHz are achievable. High Speed Viterbi Core: SiWorks has extended the architecture of its silicon verified 802.11a/g Viterbi decoder for high speed FPGA operation. The increased throughput of the core allows FPGA operation beyond 140 Mega samples/s with full flexibility on the choice of traceback depth and soft-decision wordlength. The core is designed for customers benchmarking their design in FPGA's and who have throughput requirements greater than 100 Mega samples/s. A benchmark for the core is provided below:
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