|
||||||||||
Hyperstone introduces RISC/DSP microprocessor in TFBGA packaging and as a macro cell for SoC designsKonstanz, Germany, February 12, 2003 - Hyperstone introduced today its RISC/DSP microprocessors in TFBGA packaging (E1-16XSB™, E1-32XSB™) and as a TSMC or UMC macro cell. According to Dr. Matthias Steck, VP of Marketing and Sales, thanks to the TFBGA packaging customers benefit from Hyperstone's extremely small package sizes. The E1-16XSB measures only 9 x 9 x 1.2 mm, while the E1-32XSB measures only 12 x 12 x 1.2 mm. One of the first applications using these packages is a camera implemented in a wristwatch. Hyperstone's RISC/DSP processor is also available as a macro cell for integration in customers' proprietary SoC designs. Customers have the flexibility to choose between TSMC's 0.18 µm process and UMC's 0.18 µm process. With 0.18 µm technology the processor can run up to 220 MHz achieving 220 MIPS or 880 MOPS, and a 1k Complex Fast Fourier Transformations is completed in less than 0.36 ms. Due to the unified RISC/DSP architecture this outstanding performance is achieved with the highest energy efficiency of approximately 2445 MIPS / Watt. "This proven energy efficiency, together with our low-cost approach, makes our core the architecture of choice for all battery-run, cost-sensitive designs", said Dr. Steck. "Our extended portfolio offers customers the flexibility to begin their designs with the TFBGA packaged processor. Later, after increasing production volumes justify the change, customers may switch to an SoC design based on our core and realize even further cost savings." Visit us at the Embedded World 2003 from February 18th to 20th in Nuremberg, Hall 12, booth 114. For more details please visit the Hyperstone web site at: www.hyperstone.com About Hyperstone AG ###
|
Home | Feedback | Register | Site Map |
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |