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Synopsys Announces Implementation and Verification IP for PCI Express TechnologyNew Additions to the DesignWare IP Portfolio Accelerate Adoption of PCI Express MOUNTAIN VIEW, Calif., February 12, 2003 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, today announced new implementation and verification intellectual property (IP) to accelerate the adoption of the PCI Express interface standard. "PCI Express promises to deliver significantly enhanced bandwidth at low cost for a wide variety of hardware platforms and applications," said Joachim Kunkel, vice president of marketing, Intellectual Property and Design Services at Synopsys. "The DesignWare® PCI Express implementation and verification IP will give the systems and semiconductor industry a low-risk path towards bringing standards-compliant products to market quickly and reliably." "Timely availability of implementation and verification IP is critical to rapid development of new technology solutions," said Jason Ziller, technology manager from Intel's Corporate Technology Group. "With the broad industry focus on PCI Express product delivery, the need for PCI Express building blocks that enable IP is acute. Synopsys' release of implementation and verification IP is a major milestone and should help rapid deployment of PCI Express technology in the industry." The DesignWare PCI Express Implementation IP Core is a synthesizable end-point solution that can be configured to address multiple applications, ranging from server and desktop systems to mobile devices. Licensees of the core will receive Verilog source code and example synthesis scripts as well as implementation guidelines for straightforward integration, including block placement information, list of critical paths, I/O driver requirements and technology requirements. The DesignWare PCI Express Core is being developed for flexibility, simplicity and reuse with a principal focus on configurability, reliability and low gate count. The DesignWare PCI Express Verification IP significantly simplifies testbench development. It includes bus functional models for endpoint and switch, and a user-extensible monitor to validate protocol conformance and measure coverage. Verification engineers can take advantage of its built-in advanced constrained-random capabilities to generate thousands of transactions and test corner-case behavior with just a few commands. Written in OpenVera™, the DesignWare PCI Express Verification IP takes full advantage of the built-in Synopsys Smart Verification technology and has been implemented to be fully functional in Verilog, VHDL, and C-based verification environments. Pricing and Availability The DesignWare PCI Express Implementation IP is scheduled for availability in the second quarter of calendar 2003. For more information about the DesignWare PCI Express solution, or the extensive synthesizable and verification IP offerings from the DesignWare family of products, please visit http://www.synopsys.com/designware. About Synopsys Synopsys and DesignWare are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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