Avery Design Announces CXL 2.0 VIP

Tewksbury, MA., January 25, 2021 — Avery Design Systems, leader in functional verification solutions today announced availability of CXL 2.0 VIP. Computer Express Link^TM (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices

Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe® 5.0 and CXL 2.0/1.1 for CXL host, Type 1-3 devices, switches, and retimers. The CXL 2.0 VIP adds key CXL 2.0 features including

• Switching
• IDE
• RAS
• QoS
• MLD for memory pooling including persistent memory
• Native PCIe endpoint enumeration
• Hot-plug
• Significant compliance tests update

The CXL 2.0 VIP also includes key features including

• Additional VIPs supporting key SoC interface protocols – CPI, CXS, LPIF
• Automatic CXL bus enumeration
• Dynamic configuration of VIP for legacy PCIe, CXL 2.0 or CXL 1.1 including CXL device types 1-3
• Full home agent with cache and snoop filter to support Type 1-2 devices and high-level load/store initiator semantics
• Realistic traffic arbitration among CXL.IO, CXL.Cache, CXL.Mem and CXL control packets.
• Unified user application data class for both pure PCIe and CXL traffic.

“We are excited to be working with leading server processor, managed DRAM and storage class memory (SCM) buffers, switch/retimer, and IP companies who are rapidly growing the CXL datacenter ecosystem in 2021 and beyond”, said Chris Browy, vice president sales/marketing of Avery. “Our collaboration with IP companies is also critical by creating a best-in-class, robust, pre-validated CXL 2.0 IP controller and PHY solutions and streamlines the design and verification process and fosters the rapid adoption of the CXL standard by the industry.” Besides CXL Avery supports the main cache coherent VIPs including CCIX®, AMBA® 5 CHI-E and ACE, and Gen-Z^TM.

“Our collaboration with Avery has been very fruitful in making sure that our CXL design IP (COMPEX™) is fully verified and compliant to the CXL specifications,” said Ravi Thummarukudy, CEO of Mobiveil. “Verifying COMPEX with Avery VIP enabled us to successfully validate it with Intel’s CXL host platform quickly. Avery has been on the leading edge when it comes to delivering the latest Industry compliant VIP solutions such as CXL, PCIe and NVMe etc. solutions. Our joint efforts have significantly reduced the time it takes for our mutual customers to integrate Design IPs in to their SOC designs and reducing their time to market and ensuring first time silicon success”.

Mobiveil’s CXL controller IP (COMPEX™) is a highly configurable, low-latency CXL controller that supports host and device modes for several high-performance applications, such as data center accelerators, memory expanders, artificial intelligence/machine learning and special applications. The COMPEX controller IP is designed for CXL 2.0 specification and supports host and type 1, type 2 and type 3 devices. COMPEX also supports dual mode where it can be configured to operate either as a host or any of the device types.

COMPEX supports up to 16 lanes on a flex bus interface and is compliant with the PIPE 5.2 specification. It provides a simple packet-based interface-to-user logic that supports 128-bit, 256-bit and 512-bit data path widths and provides a low-latency path for easy integration into a customer ASIC. An implementation can choose one of the datapath widths based on the number of lanes and target technology to get low-latency and optimized power consumption from COMPEX controller. For CXL.io, COMPEX uses Mobiveil’s PCI-SIG® compliant GPEX™ controller and adds highly efficient and configurable CXL.mem and CXL.cache layers for a low-latency coherent path.

Availability & Additional Resources

CXL VIP for CXL 2.0/1.1 is available today.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

About Mobiveil, Inc.

Mobiveil is a fast‐growing technology company that specializes in development of Silicon Intellectual Property (SIP), platforms and solutions for networking, storage and enterprise markets. The Mobiveil team leverages decades of experience to deliver high‐quality, production‐proven, high-speed serial interconnect SIP cores, and custom and standard form factor hardware boards to leading companies worldwide. Mobiveil is headquartered in Silicon Valley with engineering development centers located in Milpitas, Calif., Chennai, Bangalore and Hyderabad, India, and sales offices and representatives located in the U.S., Europe, Israel, Japan, Taiwan and the People’s Republic of China