SoC designs drive quest for short test times

SoC designs drive quest for short test times
By Stephan Ohr, EE Times
August 20, 2001 (11:46 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010816S0077

Increasingly, chip designers are getting together with test engineers in an effort to shorten the all-important time-to-market for new-generation systems-on-chip. Not only are designers getting involved with test system development, but automatic test equipment makers are also lending their expertise to the design-verification environment. It's important to verify not just that a monster chip will function as its designers intended, but also that each and every device coming off the production line meets the designated specs.

Two trends mark the crossover between design and test. One is the tendency to conceptualize test as a design activity, and encourage designers to create production test programs (or at least specify the contingencies) in the design environment. The other is use of built-in self-test (BIST) as a vehicle for improving testability and shortening valuable time a chip spends on the production tester.

The trends are especially noteworthy for mixed-signal ICs, which process not only patterns of ones and zeroes, but also voltages and currents with levels that can change instantaneously. With mixed-signal devices, even communication ICs, the design engineer and the test engineer must share intimacies on parametrics. Adding analog line drivers, receivers, data converters, phase-locked loops and clock recovery circuits to a system-on-chip further complicates an already complex test process.

Even without the presence of mixed-signal elements, testing the new breed of system chips can be a cumbersome-and expensive-proposition. Shrinking CMOS geometries have made it possible to build devices with 50 million transistors on one chip. But once the IC is put into production, every single one of those transistors-not just 49,999,999-must be functional or you throw that chip away. It is time-consuming and expensive to exercise 50 million transistors on a $15 million production tester, yet no manufacturer wants to risk its go od name by sending potentially faulty units out into the field.

The goal of modern production testing is to minimize time on the tester. Specialized algorithms help test engineers get to the performance root of a microcontroller, DSP or data converter, or an application-specific standard product like an MPEG decoder, disk-drive read channel or Ethernet physical-layer device. But highly customized parts increasingly demand customized test solutions, demanding more time from the engineer who must program the tester as well as increasing the duration the chip must reside on the machine.

User interface matters
As contributors to this issue of Signals point out, a number of factors can contribute to test times for complex devices. George Rose, business-unit manager in Teradyne Inc.'s Multimedia Broadband Unit, says that a graphical programmer interface that allows engineers to specify data sheet parameters is among the easiest ways to create a parametric test routine.

LogicVis ion, based in San Jose, Calif., has long been an advocate of built-in scan test. Marketing manager James Fujimoto argues that smart partitioning between BIST and test program development eases the burden on the tester. For his part, Jon Turino, product-marketing manager for Fluence Technology, says that scan testing is useful for continuity testing, but functional testing is required to verify the parametrics of a device-especially its ac characteristics. Production testing, however, will utilize combinations of scan, BIST and functional testing to verify performance at speed.

Additional contributors on this topic, whose articles appear on the Planet Analog Web site (www.planetanalog.com), include Lon Hintze of Agilent Technologies and Jeff Teza of Syntricity.