MoSys' 1T-SRAM embedded memory silicon-verified on 90-nanometer process

Highest density memory for standard logic process proves scalability of MoSys' technology

SUNNYVALE, Calif. (March 10, 2003) MoSys, Inc. (NASDAQ: MOSY) the industry's leading provider of high density SoC embedded memory solutions today announced that MoSys' 1T-SRAMÒ memory technology has now been silicon-proven on the 90-nanometer generation standard logic process.

"The silicon verification of 1T-SRAM technology on the 90-nanometer manufacturing process is another step which proves the continuing excellent scalability of 1T-SRAM memory since we first introduced it on the 0.25-micron standard logic process in 1999," commented Mark-Eric Jones, MoSys' vice president and general manager for Intellectual Property. "With the highest density for embedded RAM on the 90-nanometer standard logic process, 1T-SRAM technology enables designers to create products that would otherwise have been impossible or uneconomic.  By working closely with leading foundries, MoSys has already proven 1T-SRAM technology on this latest process generation, allowing designers to incorporate 1T-SRAM memory into their product designs with confidence."

1T-SRAM memory uses a 0.61 micron2 bit cell design to achieve the industry's highest embedded memory density of 1.1 mm2 per megabit for the 90-nanometer standard logic process.  This allows designers to easily integrate over 100-megabits of high performance embedded memory on a standard logic device, for next-generation System-On-Chip (SOC) products.  By adopting MoSys' recently announced 1T-SRAM-QÔ technology, even higher densities of 0.55mm2 can be achieved using the reduced 0.28-micron2 bit cell design in the 90-nanometer process generation.

By incorporating MoSys' patented Transparent Error CorrectionÔ (TECÔ) technology as standard for the 90-nanometer implementation of 1T-SRAM memory, the user avoids the cost of laser repair for large embedded memories while benefiting from quality advantages on yield, reliability and soft error rate.  The measured soft error rate for MoSys' 1T-SRAM test chips on the 90-nanometer standard logic process is under 4 failure-in-times (FITs) per megabit.

About MoSys
Founded in 1991, MoSys (NASDAQ: MOSY), develops, licenses and markets innovative memory technologies for semiconductors. MoSys' patented 1T-SRAM technologies offer a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM memory results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic manufacturing processes.       1T-SRAM technologies also offer the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it an ideal technology for embedding large memories in System on Chip (SoC) designs. MoSys' licensees have shipped more than 50 million chips incorporating 1T-SRAM embedded memory technology, demonstrating the excellent manufacturability of the technology in a wide range of silicon processes and applications. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys' website at http://www.mosys.com.

1T-SRAM® is a MoSys trademark registered in the U.S. Patent and Trademark Office.  All other trade, product, or service names referenced in this release may be trademarks or registered trademarks of their respective holders.