Introducing superfast serial interfacing with JESD204B Tx - Rx PHY IP Cores in 12nm, 28nm and 40nm for all type of ADC/DAC and ASIC/FPGA connections

October 3, 2022. – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s Silicon Proven and mature JESD204B Tx & Rx PHY IP Cores in major Fabs in popular process nodes 14nm, 28nm and 40nm along with matching JESD204B Tx-Rx Controller IP Cores. The JESD204B offering has seen mass production in various chipsets.

JESD204B Tx-Rx PHY IP Cores interface provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. The JESD204B PHY has full featured transceiver capabilities along with standalone Tx and Rx availability. The PHY in 14nm, 28nm and 40nm supports a data rate of 1Gbps to 16Gbps per lane.

The JESD204B PHY IP cores in 14nm, 28nm, 40nm supports multiple lanes transceiver, with this version including both receiver and transmitter. It is also available as Transmitter or Receiver only version according to the needs of the customer. The multiple lanes come with a diverse 40bit/32bit/20bit/16bit selectable parallel data bus with independent per-lane power down control. The afore mentioned per-lane power down control is complemented by an Integrated LC-tank PLL and Ring OSC PLL that allows for a very low power consumption making it feasible for implementation for a wide range of products.

The JESD204B PHY and Controller IP Cores complete solution boasts additional Programmable transmit amplitude, Programmable 3-tap feed forward equalizer (FFE) and an Embedded receiver equalization (CTLE and DFE) to compensate insertion loss for a realiable and proven solution that also has a built-in self-test with multiple pattern generation and checker for production test.

The JESD204B PHY IP cores has a flexible reference clock frequency range with an integrated on-chip differential 100-ohm termination for the same. It can support both Flip Chip Package and Wire Bonding Package.

JESD204B Tx-Rx PHY IP cores along with JESD204B Tx-Rx Controller IP cores has been used in semiconductor SoCs for Smartphones, Personal Computers, Recording Devices, digital TVs, Multimedia devices and other industrial uses…

In addition to JESD204B PHY IP Cores, T2M ‘s broad silicon Interface IP Cores Portfolio includes USB, HDMI, Display Port, MIPI (CSI, DSI, UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com