SoCMosaic Custom Chip Technique Delivers on Promise to Slash Total Design Time; New Chip Taped Out in Just 4 Months
SAN JOSE, Calif., April 21, 2003 -- Toshiba America Electronic Components, Inc. (TAEC)* today announced a new ARM®-based reduced instruction set computer (RISC) networking controller, the first offering in its SoCMosaic™ custom chip program of system-on-chips (SoCs). Designated T6TC1XB-0001, the new device was developed specifically for low-cost networking and consumer convergence applications, including access points, home gateways, small office/home office routers, thin client internet-capable devices, networked peripherals, multimedia application servers and multi-channel voice-over-IP phone sets. Customers can also use the new device as a template to design cost-effective SoCMosaic custom chip derivatives with a six-month turnaround time.
"The T6TC1XB-0001 is a resoundingly successful proof-of-concept of the SoCMosaic custom chip methodology. We taped it out in just four months and produced a finished chip to take to market in only six months from project start," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC. "We believe ours is the first ARM926EJ-S-based networking controller to offer the right level of performance and features for cost-sensitive networking and consumer convergence applications. We anticipate that customers will design the T6TC1XB-0001 into their products to gain time-to-market advantages and then follow that up with a fast-turn SoCMosaic custom chip derivative to reap dramatic cost reductions."
The new device provides two Ethernet Media Access Controller (MAC) ports and a Peripheral Component Interconnect (PCI) controller that can act as a host bridge controller or as a multi-function PCI adapter. Integrated system peripherals, a distributed Direct Memory Access (DMA) architecture and a synchronous dynamic random access memory (SDRAM) controller provide everything needed to run operating systems such as Linux or a real-time operating system (RTOS) with headroom left for tasks like compression, packet processing or voice-over-IP. A high-throughput bus design assures maximum system performance.
Mr. Tobias noted that the new chip serves as a bridge to customization for low- and mid-volume customers in the 10,000- to 200,000-pieces per year range. Designers can develop a unique version of this device with a different set of peripherals or their own custom logic in the same approximately six-month turnaround time as that achieved by the T6TC2XB-0001. He said that the SoCMosaic custom chip approach is also the most cost-effective way to develop a custom SoC: "The twin benefits of fast speed-to-market and low design costs make SoCMosaic custom chip a compelling solution for customer-driven SoCs, even in low-volume applications."
Key Features
Key features of the networking controller are as follows:
- Integrates a single 150 megahertz (MHz) ARM926EJ-S CPU with 16K-bytes instruction and 16K-bytes data caches.
- ARMv5TEJ RISC architecture with built-in 16-bit Thumb instruction set.
- DSP instruction extensions.
- ARM Jazelle™ technology Java bytecode acceleration.
- Incorporates a high-performance, on-chip bus running at the same speed as the processor.
- Features a distributed DMA architecture that gives each device its own DMA.
- Integrates an 8K-byte local scratch pad static random access memory (SRAM) to speed up packet processing and other data-intensive operations.
- Contains dual 10/100 Ethernet MACs connected to a high-throughput bus to ensure sufficient packet traffic bandwidth to the high-speed SDRAM.
- Each MAC unit includes dual 2K-byte First In/First Out buffers, one each for transmit and receive.
- Incorporates a PCI controller for further expansion.
- Supports up to three cards in host mode.
- Serves as a multi-function PCI controller in adapter mode.
- Integrates a high-performance SDRAM controller.
- Permits up to two banks of low-cost SDRAM, four banks with interleaving.
- Incorporates a set of system-level peripherals along with a 16-bit external bus for connecting memory and input/output (I/O) devices.
- Runs the broad range of operating systems, application software and development tools available for ARM processors.
- Available development board for product evaluation and software development includes a board support package for Linux and RTOSs.
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Pricing and Availability
Samples of T6TC1XB-0001 will be available in July 2003 at $14.25 per piece in 1,000-piece quantities. Mass production is slated for the third quarter of 2003.
Technical Specification Summary:
| Part Number | T6TC1XB-0001 |
| Process | 130 nanometer process |
| CPU | ARM926EJ-S |
| Operating Power Voltage | 3.3 Volts (V), 2.5V and 1.5V external supplies, 1.5V internal core voltage |
| Maximum Operating Frequency | 150MHz with 500 milliwatts power dissipation |
| On-Chip Cache Memory | Instruction Cache: 16K-bytes
Data Cache: 16K-bytes
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| RAM | 8K-bytes local scratchpad SRAM |
| MACs | Dual 10/100 Ethernet MACs, fully IEEE802.3- and 802.3u-compliant |
| On-Chip Bus | Runs at same speed as processor
Distributed DMA architecture
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| PCI Controller | Compliant with PCI specification 2.2
33MHz, 32-bit bus
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| SDRAM Controller | Two banks of SDRAM, up to 150MHz |
| External Bus Controller | 24-bit address
Programmable chip selects for up to 8- or 16-bit random access memory, read only memory, Flash or I/O devices
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| System Peripheral Block | Universal Asynchronous Receiver/Transmitter
Watchdog timer
Interrupt controller
Dual 32-bit timers
8-bit General Purpose Input/Output port
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| Package | 352-bump plastic ball-grid array |
About SoCMosaic Custom Chip
SoCMosaic™ custom chip is a platform-based design approach for intellectual property (IP)-rich designs that can reduce time-to-market for a custom SoC to as little as six months. SoCMosaic custom chip achieves rapid development of complex SoC designs by using commodity IP blocks, standardized bus interfaces, a scalable bus system, a register-transfer level (RTL) test bench and high-level, cycle-accurate C simulation. Pre-verified, pre-tested commodity and differentiating IP allows maximum flexibility. System level support includes hardware and software design (with firmware and middleware) running on cycle-accurate system-level models for early development of application software. The V.1 platform, available now, is aimed at embedded applications that combine application-specific functions with a single control processor running Linux or an RTOS, for example, low-end networking and consumer applications.
*About TAEC
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the third largest semiconductor company worldwide in terms of global sales for the year 2002 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.
