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NEC’s New TCP/IP Offload Engine Powered by 10 Tensilica Xtensa Processor CoresUpdate: Cadence Completes Acquisition of Tensilica (Apr 24, 2013) Highly Optimized TOE Speeds the Throughput of IP-Based Storage Systems
Santa Clara, Calif., May 12, 2003 – Tensilica®, Inc., the leading provider of configurable and extensible processors, today announced that NEC Corporation has developed its first TCP Offload Engine (TOE) integrating 10 Xtensa® processor cores on a single chip. NEC's TOE (TCP offload engine) chip, also announced and made available today by NEC, has been designed to speed the throughput of storage area network (SAN) and network-attached storage (NAS) systems.
"The market shift toward Ethernet-over-IP and iSCSI as the preferred transmission protocols for storage systems is putting new demands on server and storage subsystem designs," said Mr. Hirooto Ono, Engineering Manager, System File Products Division, NEC Corporation. "A general-purpose CPU – even a monolithic IC running at several GHz – does not have the necessary horsepower. So application-specific TCP/IP offload engines are required. However, designing a multi-million-gate ASIC completely from hardwired state machines for such a diverse protocol as TCP/IP is a monstrous challenge. Tensilica's Xtensa core offered us a superior design alternative – the benefits of a programmable, processor-based solution with the performance of a dedicated, rigid logic solution. By designing the TOE processor around 10 Xtensa processors optimized with storage networking specific instructions of our own design, our device is both highly optimized and programmable."
"Having established itself as a premier supplier of both high-performance networking chips and equipment, NEC brings a well-rounded perspective to the design of advanced storage SOCs," said Bernie Rosenthal, senior vice president of sales and marketing for Tensilica, Inc. "By using our automated process to generate Xtensa cores matched exactly to each part of the application, NEC achieved the performance this product required. Additionally, they were able to create this chip with significantly reduced engineering resources and design time."
About the TOE Chip
Starting with the Xtensa processor's base instruction set, NEC added storage-networking-specific instructions, using the Tensilica Instruction Extension (TIE) language to create an even more optimized instruction set that performs powerful compute-centric acceleration in very few cycles.
About Tensilica's Xtensa Architecture
Using the Tensilica Instruction Extension (TIE) Language, customers are able to add an unlimited number of user-defined instructions to the processor. Tensilica's processor generator technology creates a complete, correct-by-construction processor solution – hardware, software environment, modeling and EDA tools – in just over an hour. Each core can be optimized for virtually any application. This has made the Xtensa platform an attractive alternative to custom logic blocks, which were traditionally designed to accompany off-the-shelf, hard-wired processor cores in order to optimize the SOC for the target application.
About NEC Corporation
About Tensilica
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