Patented ViaMask technology and ViaPath physical design software lower mask costs; both are available in new design kit
Research Triangle Park, NC – May 12, 2003 – ViASIC Inc. today announced a new one-mask modular array architecture, new physical design software for modular arrays, and a design kit that includes everything a design team needs to implement a TSMC one-mask design, including the software, a technology license, and the master tile.
ViaMask™ is ViASIC's new, patented one-mask architecture that slashes non-recurring engineering (NRE) costs while preserving chip performance, density, and low power consumption for 0.18 and 0.13 micron foundry processes.
ViaPath™ is the first commercially available physical design tool that can place, optimize, and route a one-mask design. ViaPath was developed in concert with ViaMask to reduce the number of custom masks required to configure logic, from the typical 20 to 28 masks to just one, with a proportional reduction in mask costs. ViaPath and the design kit effectively enable reasonable per part costs for projects that previously were infeasible, creating new opportunities and markets.
"For chips that ship less than a million units, standard-cell methodologies are not the smartest way to implement digital logic, and FPGAs have performance issues and are too expensive for any type of significant volume," said Max Lloyd, president and CEO of ViASIC. "People who design standard-cell chips are getting killed on mask costs and high minimum quantities, especially for market-driven designs that evolve over time and require respins."
Lloyd added, "One-mask modular arrays are a great solution for many of today's daunting design, manufacturing, and business problems; and may be the next big industry trend. We offer a complete solution that is attractive for manufacturers, yet enables designers to quickly and inexpensively build, add to, or change designs."
Bill Cox, chief technology officer of ViASIC, said, "ViaMask approaches standard-cell performance with better density, lower NRE costs, and faster time to market than gate arrays. Our technology could allow modular array technologies such as those from LSI Logic and NEC to reduce customized masks per design by 4x or more while improving performance."
The ViaMask architecture fills the growing gap between field-programmable gate arrays (FPGAs) and increasingly costly and complex standard cell application-specific integrated circuits (ASICs). Compared to standard-cell ASICs, ViaMask offers lower mask costs, easier design flows, and better time to market. Compared to FPGAs, ViaMask offers much better part prices, better densities, faster clocks, and better power consumption.
ViaMask is a perfect solution for any company needing multiple versions of a design or lower NREs. One target application is the flexible standard product market where companies can use the ViASIC design kit to build a family of common products in a single base chip or system-in-a-package.
ViaPath takes a gate-level netlist and maps it into the one-mask architecture; optimizes the design for timing including buffer insertion and gate resizing; performs clock tree routing, antenna checking, and automatic repair. The software runs on MS Windows, Linux 7.3 and Solaris operating systems. ViaPath takes in industry-standard input formats of Verilog, VHDL, and .sdc; and generates the physical design and SDF for back-annotation timing verification.
Price and Availability
The Flexible Standard Product Design Kit is a complete system for implementing digital logic at processes of 0.18 micron and below with a single mask, giving designers the flexibility to inexpensively add or change logic. The TSMC 0.18-micron design kit is available for purchase now; U.S. pricing starts at $345,000. Design kits for the TSMC 0.13-micron process and UMC 0.13-micron process are expected to be available in the near future. U.S. pricing for a 0.13-micron design kit is expected to start at $585,000.
