'Synthesis engines' roll out to speed PLL design

The Barcelona synthesis engines include a clock generator, named Miro, after the Spanish painter Joan Miro, and a topology platform, called Prado, after the Madrid art muse um. As a builder of serial-ATA and digital video interface devices, Matsushita "consumes a large number of PLLs," Nandra said.

For these applications, the PLL inputs can vary from 1 to 25 MHz and from 1 to 150 MHz. On-board voltage-controlled oscillators can range from 200 MHz to 2 GHz, Nandra said. A low-frequency PLL-useful for computer graphics, DVD screen synchronization and mobile-phone displays-uses a 15-kHz to 250-kHz VCO.

The PLLs can be optimized for low jitter, low power consumption and a wide range of operating frequencies, Nandra said. They are also tweaked to yield well over a variety of process, temperature and voltage corners. This will likely meet the majority of Matsushita's clock-generation and synchronization PLL requirements over the next several years, he claimed, and represents a radical change in how Matsushita creates PLLs for its system-on-chip projects.

"Why build an inventory if you can create fresh IP?" Nandra asked.

In a prepared statement, Yutaka Katabe, group manager of Matsushita's System LSI Technology Development Center, suggested that Barcelona's synthesis tools reduce PLL development time to a matter of hours. "It will have a major impact on our analog productivity, as well as the deployment of our designers to high-value projects," Katabe said.

Barcelona Design has shifted its emphasis over the years from online synthesis tools to analog IP and fields a catalog that includes op amps and RF circuits. The company was founded in 1999 and is financed by Sequoia Capital, Foundation Capital and Crosslink Capital.