Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Hsinchu, Taiwan – Oct 21, 2024 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ 46-series processor family with 4 members. The first member, AX46MPV, a new 64-bit multicore superscalar vector processor IP, is the third generation of the award-winning Andes Vector core. While it maintains the same 8-stage dual-issue pipeline as its predecessor AX45MPV, it incorporates numerous new features such as dual load/store units, private L2 cache, an extended VLEN, Andes Matrix Multiply Extension, and RVA22 profile support. Except vector and matrix support, the second member, AX46MP, has the exact same features as the AX46MPV while the third member, A46MP, and fourth member, A46MPV, are the 32-bit versions of AX46MP and AX46MPV. This makes the 46-series ideal for network processors running Linux, high-performance embedded controllers requiring high memory throughput, and large-scale AI/ML applications.

The AX46MPV enhances SpecInt2006 performance by over 15% compared to the previous generation AX45MPV, thanks to its newly designed memory subsystem. The private L2 cache significantly reduces memory latency while the dual load/store engine eliminates memory bottlenecks in memory-bound computation kernels. It supports up to 16 cores in the same cluster, featuring cache coherence and a shared L3 cache with doubled capacity of the AX45MPV. Additionally, the AX46MPV provides TrustZone-level security with ePMP and IOPMP, accompanied by a pre-integrated software solution.

The AX46MPV introduces several enhancements for AI/ML, including longer 2048-bit vectors, new Andes Matrix Extensions to efficiently speed up GEMM performance, and greatly improved High-Bandwidth Vector Memory (HVM) interface supporting outstanding requests and out-of-order responses. A high-performance HVM controller serving up to 16 cores and DMA accesses with 64 memory banks is optional for licensing. The AX46MPV now also includes BF16 full arithmetic mode as a standard feature. Additionally, the award-winning Andes Automated Custom Extension™ (ACE) is available in the 46-series, featuring customized vector instructions (ACE_RVV) with enhanced pipeline and Streaming Port (ASP).

“We are thrilled to introduce the 3rd generation of the Andes Vector series, further strengthening our leadership in the AI SoC market,” said Dr. Charlie Su, President and CTO of Andes Technology. “Our NX27V and AX45MPV have been highly successful in high-performance AI SoC applications. The AX46MPV, boosted with both compute performance and memory bandwidth, is intended to bring the new-generation AI SoCs to the next level of compute density. Additionally, with enhanced capabilities in Linux, security, and AIoT, the highly configurable 46-series is a well-rounded solution with balanced performance, power, and area”

The AndesCore™ 46-series processor IP’s, 64-bit AX64MP(V) and 32-bit A64MP(V), can be configured from one core up to 16 cores. It is to be available for lead customers in Q1 2025 through the early access program and for general customers in Q2 2025. For further information about the Andes 46 series and Vector processors, please contact Andes Technology.

About Andes Technology

Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com.