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Chip Express Announces Successful Deployment of Structured ASIC Products Incorporating ParthusCeva PLL IPSan Jose, Calif - July 03, 2003 - ParthusCeva, Inc. (Nasdaq: PCVA, LSE: PCV) the leading licensor of Digital Signal Processor (DSP) cores, platform-level and PLL IP to the semiconductor industry, and Chip Express, the leading manufacturer of late-stage programmable Structured ASICs, announced today the successful deployment of the Chip Express 0.18um CX5000 family of Structured ASIC products, incorporating ParthusCeva 0.18um UMC-based PLL IP. The Chip Express 0.18um CX5000 product family utilizes the combination of an advanced metal programmable Structured ASIC and optimized EDA system to implement high-performance ASIC designs. ParthusCeva's innovative metal mask programmable PLL provided the flexibility required to fulfill the 0.18um CX5000 Structured ASIC design objective of reducing application tooling costs and design turnaround time. "When we explained our Structured ASIC objectives for the CX5000 family, ParthusCeva's PLLXpert Online PLL compiler provided us with a right-first-time solution optimized exactly to our design requirements," said Stephen Bateman, Vice President of Engineering and R&D at Chip Express. "We are very happy with the first-time success of their solution." "Products addressing the burgeoning Structured ASIC market have some very specific technical challenges. We were able to meet Chip Express' performance and flexibility needs using our silicon proven PLLXpert compiler PLL IP, and we were able to very quickly compile a PLL to meet their aggressive schedule," said Kieran Flynn, PLL Business Manager at ParthusCeva. "We are pleased with the successful production deployment of our solution." CX5000 0.18um Structured ASIC The CX5000 comprises a family of pre-configured platform masterslices that contain varying amounts of general-purpose logic, fast memory, advanced I/Os, clock synthesis and phase management macrocells. When combined with a mix of popular third-party tools and custom designed point EDA solutions, the CX5000 provides not just Structured ASIC hardware, but also a complete ASIC Platform from which to develop today's advanced SoC ASICs. PLL Business Unit of ParthusCeva, Inc. In addition, through PLLXpert Online, a web based PLL compiler, designers can either create a custom PLL or alternatively download an existing PLL reference design that can be fine-tuned by the designer for a specific application. No prior training, in-depth PLL design knowledge or additional EDA tools are required. PLLXpert Online delivers a complete design kit including datasheets, verilog models, and the necessary files for logic synthesis, place and route. These deliverables enable the designer to fully validate the integration of the PLL into the IC by optimising the PLL until it meets system requirements with immediate GDSII delivery on final demand. For more information, visit ParthusCeva's PLLXpert Online website at http://www.pllxpert.com. About Chip Express About ParthusCeva ParthusCeva Safe Harbor Statement
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