| San Mateo, Calif. — Startup IPextreme Inc. (Campbell, Calif.) is offering a synthesizable, drop-in block that performs Bluetooth baseband functions, connects directly to a variety of RF chips and isolates the host CPU's software stack from any real-time interrupts. In addition, the core includes several novel design choices that reduce the amount of work and risk involved in system-on-chip (SoC) integration. Perhaps the most unusual aspect of the XBlue 1200 core is the way it is interconnected with the rest of the SoC in which it dwells. IPextreme provided a hardware UART in the intellectual property (IP), intending it to be connected to a UART elsewhere on the SoC through the usual two-line serial interface. "The single-chip Bluetooth radios and the older two-chip sets connected to the host through a UART interface, simply because it is fast enough," said Warren Savage, president and chief executive officer of IPextreme (www.ip-extreme.com). "When we started designing the XBlue core, we looked at that and realized that there were important reasons to maintain the UART interface even when the baseband block was on the SoC with the host CPU." To start with, Savage said, the software protocol stacks are written expecting to see a UART. Giving them a UART avoids any recoding and the risks of introducing obscure timing issues. Second, having a pair of UARTs between the host bus and the baseband hardware provides some useful data buffering — a major issue in the Bluetooth world, where latencies can be substantial. Finally, the UART interface reduces the signal routing and timing analysis necessary to integrate the block to the level of trivia. For the UART interface to be effective, it is necessary to encapsulate all the time-critical loops within the baseband block itself. This is also a big win for the SoC software team, as it means the team will not have to add tasks with critical latencies to its task mix, further taxing the real-time operating system. It is accomplished by incorporating a 68HC11-compatible 8-bit microcontroller in the core. "The HC11 is excellent for this application," Savage maintained. It is simple, and its 8-bit bus doesn't burn huge amounts of energy doing the bit-level operations that are necessary in a Bluetooth baseband. "So the power dissipation is far less than would be the case if we were trying to do the time-critical tasks on a 32-bit core. Plus, the architecture is much more friendly to C programming than is an 8051," Savage said. Moreover, the core is able to interface to multiple kinds of RF chips. At design time, the licensee specifies as a synthesis parameter which RF chips will be used; only the necessary circuitry for those interfaces will be synthesized. Then, at power-up of the installed SoC, the XBlue interface automatically detects which of the chosen chips it is actually connected to, and configures its interface accordingly. Hence the same SoC can support different RF chip vendors with a simple change in board art. It is a very interesting combination of design time configurability and autoconfiguration. Also, IPextreme has gone to great lengths to reduce energy consumption, Savage said. "Bluetooth is a protocol with lots of modes and lots of dead time. Most of the time the radio isn't actually doing anything. This makes it very important that you be able to get into and out of an effective sleep mode quickly." Separate gated clock regions for the HC11, the voice codec, the UART and the baseband hardware engine provide an ability to shut down and restart individual pieces of the IP as necessary. The fact that interrupt-driven tasks are all done in the XBlue also gives a system designer the opportunity to put the host CPU to sleep more freely even when the Bluetooth interface is live. "There's no interrupt every 625 microseconds just to keep the link up," Savage said. "We handle that internally." The result, he said, is a complete interface power reduction of about 50 percent compared with competitive solutions. The XBlue block has been implemented in Taiwan Semiconductor Manufacturing Co. Ltd.'s 130-nanometer CMOS using Artisan Components Inc.'s G libraries. The block is about 4.75 mm2, with 80k gates of logic and the associated RAM and ROM, which are separate from the logic core. The size of the core will vary from around 64k gates up to a little over 104k gates, depending on how many voice channels (up to three) the licensee specifies and whether an optional encryption block is included. The IP is delivered in IPextreme's XPack, which includes RTL, guidelines and documentation, verification environment and firmware. | 
