Lattice Expands its Revolutionary ispXPLD Device Family with 1,024 and 256 Macrocell Members

ispXPLD 51024MX and ispXPLD 5256MX Now Production Released

HILLSBORO, OR - AUGUST 4, 2003 - Lattice Semiconductor Corporation (NASDAQ: LSCC), the inventor of in-system programmable (ISPTM) logic products, today announced the release of two additional members of its revolutionary in-system programmable eXpanded PLD (ispXPLD) family, the ispXPLD 51024MX and ispXPLD 5256MX devices. The ispXPLD 51024MX features up to 1,024 logic macrocells and up to 512 kilobits of on-chip memory and represents the largest member of the family. The ispXPLD 5256MX provides up to 256 logic macrocells and up to 128 kilobits of on-chip memory and is the smallest member of the device family.

The ispXPLD architecture is the first PLD architecture that allows users to efficiently trade off fast logic and block memory resources. The unique architecture offers Multi-Function Blocks (MFBs) that can be independently used for logic functions (up to 32 macrocells per MFB) or memory functions (up to 16 kilobits per MFB), yielding up to 1,024 logic macrocells or 512 kilobits of on-chip memory on a single device, equivalent to 300K system gates. The ispXPLD 51024MX device delivers 5.2ns pin-to-pin delay (tPD ), 3.8ns clock-to-output delay (tCO ), 3.0ns set- up time (tS) and 235MHz operating frequencies (fMAX). The ispXPLD 5256MX device provides 4.0ns tPD, 2.8ns tCO, 2.2ns tS, and 300MHz fMAX.

The ispXPLD 5000MX family is available in 1.8, 2.5 and 3.3 Volt power supply versions, designated the ispMACH 5000MC, 5000MB and 5000MV series respectively. The devices are offered in 256, 512, 768 and 1,024 macrocell-equivalent densities with 141 to 381 user I/O, corresponding to 75K to 300K system gates. Programmable sysI/OTM interface capability provides flexible advanced I/O standard (GTL+, HSTL, SSTL, LVDS, etc.) support, as well as 5 volt tolerant I/O. Advanced non-volatile E2CMOS® silicon technology, combined with proprietary circuit design techniques, provides standby power consumption as low as 36 milliwatts per device for power-sensitive applications. Each device also incorporates Lattice's sysCLOCKTM phase-locked loops (PLL) capability for high-performance on-chip clock synthesis.

The mix of system-level functionality, memory and logic allows the ispXPLD devices to address mainstream system functions previously served only by FPGAs or ASICs. Potential application areas include high-performance bus bridges, intelligent backplane interfaces and protocol processors. At 1,024 macrocells, the ispMACH 51024MX is the highest density product term-based logic architecture available in the industry, delivering wide decoding capability and predictability of timing. With this new 1,024 macrocell density point, system- level functions can now take advantage of the expanded logic density along with other ispMACH 5000MX device features: flexible on-chip memory, PLLs, sysI/O interface, and ispXPTM technology with instant-on capability that eliminates external PROM requirements.

Multi-Function Block Implements Macrocells or Memory Efficiently
The homogeneous ispXPLD architecture consists of a number of uniform Multi-Function Blocks interconnected by a single- level, high speed programmable Global Routing Pool (GRP). The GRP also connects the MFBs to the I/O cells. Devices in the ispXPLD 5000MX family integrate from 8 to 32 MFBs into a single device. Each MFB within an ispXPLD device can be programmed independently to implement 32 macrocells of SuperWIDETM logic, an 8 kilobit Dual Port RAM, a 16 kilobit Single Port RAM or FIFO, or a 128 by 48 bit Content Addressable Memory (CAM). Dedicated FIFO control logic is included on-chip so programmable resources are not consumed when providing these memory control functions. While the basic logic block configuration supports up to 68 logic inputs in a single level of logic, cascading MFBs allow the devices to support functions of up to 136 inputs without incurring an additional level of logic delay, further raising the bar for a wide logic architecture.

ispXP Technology - Non-Volatile and Infinitely Reconfigurable
Lattice's new ispXP technology enables its ispXPLD family (as well as its ispXPGATM FPGA devices) to combine the programmability benefits found in both E 2 PROM-based non- volatile PLDs as well as SRAM-based reconfigurable FPGAs. As a result, the devices feature: (i) "instant on" operation at system start-up, allowing them to support critical system "heartbeat" functions without external initialization; (ii) non-volatile in-system programming, giving higher integration through the elimination of an external boot PROM; (iii) enhanced design security through the elimination of external programming bit streams; and, (iv) infinite reconfigurability via an 8-bit microprocessor port or JTAG boundary scan port for the ultimate in-system reprogrammability.

Design Tools
The ispXPLD 5000MX family is supported by Lattice's new ispLEVERTM v3.0 design tools. The ispLEVER tools, Lattice’s platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispXPLD devices while maximizing resource utilization. This is achieved through timing driven placement and routing coupled with optimized synthesis support from vendors such as Mentor Graphics/Exemplar and Synplicity. Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export. The ispLEVER software is available in PC as well as UNIX workstation versions. The ispLEVER design tools, including VHDL and Verilog synthesis tools, are available now for download from the Lattice website at www.latticesemi.com/products/devtools.

Price and Availability
Production devices are available now for the ispXPLD 5256MX and ispXPLD 51024MX devices, along with the previously announced ispXPLD 5512MX, in both Commercial (0 to 70°C ambient) and Industrial (-40 to +85°C ambient) temperature grades. The ispXPLD 5256MX devices are available in the 1.0mm ball pitch 256 fine pitch Ball Grid Array (fpBGA) package, and the ispXPLD 51024MX in 484 fpBGA and 672 fpBGA packages. Pricing for the ispXPLD 5256MX in volumes of >10,000 pieces starts at $9.50 and the ispXPLD 51024MX at $42.00. The last member of the ispXPLD 5000MX family, the ispXPLD 5768MX, is scheduled for release later this year.

About Lattice Semiconductor
Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGAs), Field Programmable System Chips (FPSCs) and high-performance ISPTM programmable logic devices (PLDs). Lattice offers total solutions for today’s system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and militaty systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268- 8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company’s Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

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