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IPCore and Cadence Collaborate to Launch Advanced Design Methodology Based on CSMC ProcessSilicon Design Chain optimized through IPCore-CSMC-Cadence Digital Design Kit for CSMC Process "IPCore is a leader in the ASIC design services market in China and has an advanced design methodology to meet design challenges down to 0.18 microns," said Yi-Chen Zhao, vice president, Engineering Services of IPCore. "On the other hand, there is a large market for mature technology worldwide, especially in China. So we chose Cadence advanced nanometer design tools as our design service platform and collaborated with Cadence to develop the digital design kit for the CSMC process in order to meet the needs of these customers for design efficiency and quality." The IPCore-CSMC-Cadence 0.5 micron digital design kit is a complete RTL-to-GDS flow that comprises all necessary steps, including logic synthesis, simulation, design implementation, RC extraction and physical verification. This flow uses products from the Cadence Encounter™ and Incisive™ platforms, including NC-Sim, BuildGates®, Silicon Ensemble®-Ultra, Assura™ and Dracula®. The flow is well-suited for 0.5-micron technology at CSMC and was designed especially for the China market. "Cadence cooperates with Chinese partners such as IPCore as part of its strategy to help grow the Chinese IC design industry," said Peter Chen, president of Cadence China and Hong Kong operations. "This kit&@151;fueled by IPCore's design methodology and Cadence digital IC design and sign-off technology, along with CSMC's process kit—further validates the Cadence digital flow and will help our customers shorten time-to-volume, reduce cost and ensure high quality." About IPCore About CSMC About Cadence Cadence, the Cadence logo, First Encounter, BuildGates and Dracula and are registered trademarks, and Encounter, Incisive and Assura are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
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