Denali and Rambus to deliver PCI Express Design and Verification Platform

INTEL DEVELOPERS FORUM, San Jose, CA – September 16, 2003 – Denali Software, Inc., the leading provider of electronic design automation (EDA) tools and intellectual property (IP) for chip interface design and verification, and Rambus Inc. (Nasdaq:RMBS), a leading provider of chip-to-chip interface products and services, today announced a collaboration agreement to deliver a comprehensive PCI Express™ design and verification platform.  This platform will incorporate Denali’s PCI Express IP core and Rambus’ advanced PCI Express™ PHY core technology.  As a first step toward ensuring interoperability with PCI Express cores, the Rambus PCI Express PHY will be verified with Denali's PureSpec verification IP suite.  This integrated platform will provide PCI Express product developers with quick design turnaround time and will ensure compliance and interoperability with PCI Express architectures.

“To ease the transition from the 66MHz PCI to the 2.5GHz PCI Express standards, chip developers require robust, silicon-proven PCI Express PHY cores,” said Jean-Marc Patenaude, marketing director for the Logic Interface Division at Rambus.  “Denali is taking a leadership role in solving the verification problem for PCI Express. Using Denali's PureSpec Verification IP enables us to verify that our PCI Express interface is compliant with the specification, and more importantly, that we are interoperable with other designs using the PCI Express standard.  This is another step toward delivering fully-tested PHY cores to our customers to help them deliver successful products to the marketplace."
 
“Rambus has delivered high-speed I/O solutions to its customers for over a decade,” said Kevin Silver, vice president of marketing for Denali. “This expertise, which is now being applied to PCI Express interconnects, has resulted in a very strong roadmap for PCI Express PHY products.  Denali is currently engaged in over 50 PCI Express design efforts with our Verification IP tools; leveraging this standard solution enables us to remove the compliance and interoperability risks for our customers and the PCI Express design community in general. Rambus' interconnect expertise, combined with our verification IP and PCI Express core, will provide the industry with a rock-solid platform for this emerging standard.”   

“As a member of technical and communications workgroups within PCI-SIG, Denali has been actively participating in the industry-wide effort to define and refine the PCI Express specification,” said Tony Pierce, PCI-SIG chairman.  “We appreciate Denali's continuous commitment to further enable PCI Express technology and accelerate adoption of its architecture.”    

Rambus is committed to continuing its leadership position as a PCI Express PHY IP provider. Rambus' PCI Express IP PHY family supports TSMC 0.13-micron and UMC 0.18-micron processes to address the needs of graphics, chipset, switch and bridge chip applications using the PCI Express standard.  The Rambus PCI Express PHY cell is available in evaluation chips that have been delivered to Rambus' customers for their system development.   In addition, Rambus offers engineering services to its customers for chip integration, package, board and system characterization, as well as test, in order to ensure success in the development and bring up of PCI Express-based chips and boards.

About Denali PCI Express IP Cores
Denali's PCI Express cores were developed and verified by IBM for use in its own ASIC's, Foundry, and Standard Product Designs.  Denali now brings this design to the broader market, and directly sells and supports application specific configurations of the core through its own channels along with its existing PureSpec™ verification IP product for PCI Express. Within Denali's IP configuration and delivery infrastructure, chip designers can efficiently configure the cores for a wide range PCI Express device options, and target the design for a variety of ASIC processes or COT flows.

About PureSpec  
PureSpec is a verification IP product used by chip designers to simulate, and verify PCI Express design interfaces. PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint, and PCI Express to PCI bridge. Within PureSpec, all protocol layers (physical, data link, transaction) of the PCI Express specification are completely modeled and can be simulated simultaneously or used separately. The product contains thousands of assertions that are monitored during simulation to ensure compliance with the PCI Express specification, and interoperability with other PCI Express devices. Injected errors and error conditions are also flagged and recovered according to PCI Express specifications. The PureSpec product is built on the proven product architecture of Denali's MMAV product, which has been used to verify complex memory interfaces for thousands of successful designs, and provides seamless integrations to all popular EDA tools and verification languages. Proven product platform, dedicated customer support, and unmatched EDA modeling and verification expertise make PureSpec the best-in-class verification IP solution for PCI Express designs. The PureSpec product is available now for customer evaluation at: www.denali.com/purespec     

About Rambus Inc.
Rambus is a leading provider of chip-to-chip interface products and services. The company's breakthrough technology and engineering expertise have helped leading chip and system companies to solve their challenging I/O problems and bring industry-leading products to market. Rambus' interface solutions can be found in numerous computing, consumer electronic and networking products. Additional information is available at www.rambus.com.

About Denali
Denali Software Inc. is the world’s leading provider of EDA tools and Semiconductor Intellectual Property (SIP) solutions for chip interface design, integration, and verification. PureSpec is the industry leading solution for verifying compliance and interoperability for PCI Express designs. Denali’s Databahn memory controller cores are licensed for use in over 80 chips and provide designers with the highest quality solution for interfacing with all new and emerging high-performance memory technologies. Denali’s MMAV product is the de facto industry standard for modeling and simulating memory during all phases of design and verification. Memory selection, memory controller configuration, and memory system performance analysis are supported through Denali’s online infrastructure at eMemory.com. More than 400 companies worldwide use Denali’s tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, please visit Denali at www.denali.com or contact Denali directly at: 650-461-7200

Denali, the Denali logo, Databahn, eMemory, MMAV, and PureSpec are trademarks of Denali Software, Inc.

Rambus is a registered trademark and RaSer is a trademark of Rambus Inc.

PCI Express is a trademark of the Peripheral Component Interconnect Special Interest Group (PCI-SIG). All other trademarks are properties of their respective owners.