|
|
|
|
|
|
 |
|||
|
Cadence Announces a Complete, Reusable Functional Verification Solution to Address System-on-Chip Designs
Cadence Announces a Complete, Reusable Functional Verification Solution to Address System-on-Chip Designs
``Verification of SoC designs presents one of the toughest challenges for verification and design engineers and can consume up to 70% of a design team's manpower,'' said Rahul Razdan, corporate vice president and general manager of the Systems and Functional Verification group at Cadence®. ``To meet this challenge, we had to look beyond the usual verification methodologies and take a solutions-based approach. As a result, we can now offer a faster, more complete, and more intuitive approach to functional verification. The bottomline is that it will allow our customers to get higher quality products to market faster.'' ``Azanda is developing multi-million-gate chips for optical networking. Because these chips must handle a wide variety of communications protocols, developing exhaustive test coverage is a major challenge. Cadence Verification Cockpit provided us with the necessary exhaustive test and functional coverage, and allowed us to verify the chip in a much shorter timeframe than possible with other tools,'' said Kaushik Patel, vice president of Engineering at Azanda Network Devices. ``Many of the errors detected by Verification Cockpit were subtle and unlikely to be detected using traditional techniques.'' Verification Cockpit Integration Increases Productivity The newly released Verification Cockpit 2.0 combines multiple tools and methodologies into an integrated, mixed-language environment that helps accelerate functional verification. It combines HDL analysis, lint, testbench authoring, transaction-level analysis, and exploration with the market-leading Cadence NC simulators, including NC-Verilog, NC-VHDL, and NC-Sim. Integrating these tools into a single unified environment can increase simulation productivity. It also simplifies debugging and reduces the number of cycles required to verify a design. Verification Cockpit is the industry's first open-standards-based functional verification environment. ``Our verification problem continues to grow as new designs increase in complexity. We immediately saw the benefit that debugging at the transaction level could bring us in addressing these complexities,'' said Frank Ghenassia, manager of CR&D Design Technology at STMicroelectronics. ``With its integrated transaction viewing, analysis, and exploration capabilities, Verification Cockpit allows us to realize these benefits on our current project, and has significantly accelerated our overall schedules.'' TestBuilder Extends C++ Into a Full-Functioned Verification Language for Production Use TestBuilder 1.1, which is available through a free download from the Internet, is a C++ class library that provides testbench authoring capabilities to create reusable, random, constraint-driven self-checking tests. It seamlessly integrates with C and C++ verification models; supports VHDL, Verilog, and mixed-language design environments; and provides integration with transaction recording and transaction-based debugging tools. It is easy to learn and provides the power and flexibility of object-oriented techniques. ``Fujitsu has selected TestBuilder for its verification environment because of its non-proprietary C++ object-oriented approach for reuse, and its ability to facilitate quality module design,'' said Masami Yamazaki, manager of the Circuit Technology Department in the Communication & Device Technology Division at Fujitsu Limited. ``TestBuilder facilitates the development and use of directed random stimulus generation and fully supports the existing environment. Since TestBuilder is released as an open-source product we believe it will continue to evolve and support the needs of our most advanced testbench environments.'' ``The power of C++ and the open-source community are expected to accelerate the rapid adoption of a common testbench language,'' said Mike O'Reilly, marketing director for the Systems and Functional Verification group at Cadence. ``Many leading-edge companies already use C++ to develop their verification environments. We're excited to offer a common library that allows them to reduce the time they spend on the development of models and utilities and gives them access to industry-standard IP. Over 2,000 downloads of TestBuilder is tangible proof of the growing interest in this product.'' Complete TestBuilder library header files and documentation can be downloaded at www.testbuilder.net. Verification Reuse Methodology and Models that Support Reuse Combined with Verification Cockpit 2.0, the Cadence Verification Reuse Methodology (VRM) facilitates verification reuse at various levels of design integration and for derivative designs. It enables reuse of testbench models in the IP/SoC supply chain and the ability to quickly construct a SoC verification environment out of pre-existing models. Gathered from extensive industry experience, Cadence VRM provides a core set of verification reuse practices that enable customers to develop and deploy reusable testbench models. Cadence has used the VRM in development of verification models for standard application-oriented interfaces. The initial offering covers AMBA Advanced High-Performance Bus (AHB) and Advanced Peripheral Bus (APB), Utopia Level 1 and 2 Tx/Rx, as well as a compliance checker for the Infiniband link layer. These models can be used to construct a verification environment for any design using these interfaces. All current Cadence verification models are built in compliance with the VRM to enable consistent reuse and fast integration. ``Cadence Verification Reuse Methodology brings to functional verification an equivalent set of practices pursued in the design reuse space. It presents the opportunity to deliver on the promise of IP reuse by reusing quality verification models from project to project and from block-level verification to system-level verification,'' said Shabtay Matalon, group director for Advanced Verification in Cadence Methodology Services. ``This leads to shorter design cycles and productivity gains by improving consistency of the verification process across the board.'' ``A standardized verification reuse strategy combined with a set of testbench models that offer both quality and consistency is important to companies like Sun Microsystems,'' said Paul Whittemore, Staff Engineer, Sun Microsystems. ``These models play a key role in verifying complex designs that comply with industry standards. We have collaborated with Cadence in the development of the VRM and in the development of VRM testbench models for Infiniband. Having a company like Cadence provide a commercially supported verification solution for Infiniband is significant because it provides a mechanism for the entire Infiniband design community to test their designs against a common measure of compliance.'' The VRM can be used with the Cadence NC-Sim simulator and will support other commonly used third-party Verilog and VHDL simulators. Pricing and Availability When sold as an add-on to Cadence NC simulators, Verification Cockpit 2.0 is priced at $25,000. TestBuilder 1.1. is free. VRM is offered as a service through Cadence Methodology Services. Cadence verification models are offered as a turnkey solution that includes one-year time-based licenses, training, support, and integration methodology service. All parts of the solution are available for delivery now. About Cadence Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With 5,700 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif. and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from www.cadence.com. Note to Editors: Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All other trademarks and registered trademarks are property of their respective holders. Contact: Cadence Design Systems, Inc. Valerie Smith, 408/428-5795 vsmith@cadence.com |
|
|
|
|
|
|
|
Home | Feedback | Register | Site Map |
|
|
|
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |