Atmel throws curve at structured ASICs

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Atmel throws curve at structured ASICs
Crista Souza
EBN

09/22/2003 10:00 AM EST
URL: http://www.my-esm.com/showArticle?articleID=15000089

As an alternative to what some are calling structured ASICs, Atmel Corp. has begun offering SiliconCity, an SoC platform consisting of an emulation board and IP on plug-in cards, rather than partially configured silicon "slices."

The approach gives ASIC and ASSP customers a low-cost way to try out processors and IP together in a real-world environment, but doesn't prearrange blocks or set a boundary on the number of gates.

"An ASIC should be what the customer wants, not what the silicon supplier wants," said Jay Johnson, San Jose-based Atmel's marketing director for ASICs and ASSPs in North America. "If you have a 1 million-gate design, do you really want to pay for 3 million gates?"

Design limits has been one of the fundamental criticisms of embedded-array architectures at the heart of the structured-ASIC movement, said Gartner Dataquest analyst Bryan Lewis, San Jose.

"Everybody's attacking this issue of design cost and IP reuse with platform-style approaches, and this is another spin on it," Lewis said. "It's not a novel concept, but it's focused. Atmel is showing they're still a serious player in ASICs, and they've got some high-volume customers using this."

One such design, a fourth-generation chip for M-Systems' Smart Disk-on-Key USB drives, demonstrates the synergy between Atmel's standard product and ASIC offerings, according to Johnson. The first generation used several off-the-shelf Atmel parts together with a small gate array, and evolved into the single-chip design unveiled last week at the Embedded Systems Conference in Boston.

SiliconCity is built on validated IP from Atmel's broad product portfolio, which includes "everthing but X86 and DRAM," Johnson said. "All our products are based on a common reuse methodology for architecture, IP, and process to reduce cycle time and cost."

By keeping its SoC efforts focused on 0.18-micron processing, Atmel plays in what Johnson called the sweet spot, where mask costs have settled to a more reasonable $120,000 from the $500,000 often quoted by ASIC suppliers for 0.18 micron.

The SiliconCity platform, designated AT91RM9200, centers on Atmel's version of ARM Ltd.'s ARM920T processor, along with the standard array of peripherals and memory. Customers can add or substitute to the platform a variety of DSP and processor cores, including the ARM926EJ-S, which integrates Java and DSP capabilities, and Atmel's recently introduced mAgic DSP, a device that delivers 1Gflop performance at 100MHz. The processors are implemented on mezzanine boards that plug into the emulation board that contains the AT91RM9200.

Additional Atmel or customer IP can be added via a 500,000-gate-equivalent Virtex-II XC2V6000 FPGA from Xilinx Inc.

For larger designs, Atmel is working with Astek Corp. to partition designs into more than one FPGA. Atmel is bundling Astek's partitioning software into its ASIC tool suite, Johnson said.

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