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Texas Instruments and Sonics Enter New Agreement for Wider Use of SMART Interconnect IP in Wireless OMAP Platform from Texas InstrumentsMountain View, Calif. — September 29, 2003 — Sonics, Inc., a leading provider of SOC (system-on-chip) architectures and SMART Interconnect IP products, today announced that Texas Instruments has entered an agreement to license Sonics' SMART Interconnect IP for use in TI's next-generation OMAP SOC designs for wireless, multimedia and other applications. The agreement includes key existing Sonics SMART Interconnect IP products such as Synapse™ 3220 peripheral interconnect IP and a next generation system-level interconnect IP now under development at Sonics. The Synapse 3220 peripheral interconnect introduced in November 2002 is already being used in several next generation OMAP SOC designs. Sonics' next generation system-level interconnect IP will be SiliconBackplane™ MicroNetwork IP interface compatible and will be tailored for low-power operation such as that required by TI's next-generation OMAP wireless platforms. "TI is the unquestioned market leader in wireless applications and we are committed to developing high-performance, low power, minimum silicon area solutions to meet their target market driven requirements," said Grant Pierce, president and CEO of Sonics. "Sonics products help TI rapidly deploy power and performance improvements across a range of OMAP platforms for next generation high-end wireless handsets and PDAs. We will use their early feedback to ensure that our next generation product is optimized for low power designs." "Sonics' SMART interconnect IP will be an important part of TI's wireless technology roadmap," said Yves Masse, chief OMAP architect and TI Fellow. "The combination of Sonics SMART Interconnect IP and TI's industry leading system-level expertise will further extend TI's performance, power and time-to-market advantages in next generation wireless and multimedia solutions." Sonics' SMART Interconnect IP enables a SOC design team to develop complex designs faster with less risk. Sonics' production proven SiliconBackplane connects complex IP blocks such as microprocessors, DSPs, hardware accelerators such as MPEG, DMA or packet processors with other standard and custom IP blocks with a high degree of silicon efficiency and high data throughput. The new interconnect IP under development will incorporate new architectural features designed to provide even greater system performance while further reducing power consumption and area. The result is an architecture and methodology for rapid redesign and development of new SOC devices using proven subsystems previously integrated using SMART Interconnect IP. The Sonics Synapse 3220 SMART Interconnect IP, already in use at TI, manages the information flow between initiator (usually host) IP cores and target (usually peripheral I/O) IP cores. It greatly simplifies on-chip wiring complexity while providing low-latency access to a large number of physically dispersed peripheral cores. Working with other Sonics' SMART Interconnect IP, Synapse 3220 uses patented protocols and a flexible architecture to improve peripheral sub-system bandwidth and efficiency while reducing SOC design complexity. Among Synapse 3220 benefits are rapid peripheral core integration and implementation, low latency data access, low power consumption with fine-grained power management (very critical to mobile applications), guaranteed end-to-end data transfer performance, and increased reusability. Sonics IP is OCP (Open Core Protocol) compliant. Sonics and TI are board members in the Open Core Protocol International Partnership (OCP-IPTM) that promotes a complete socket standard to ensure rapid creation and integration of interoperable intellectual property cores. Sonics has committed that all products based on its new architecture will be fully OCP-compliant. About Sonics, Inc. SiliconBackplane and Synapse are trademarks of Sonics, Inc. All other trademarks are the property of their respective owners.
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