MIPS32™ 24K™ Core Family Features 550 MHz Optimized Design Flows and System-Level On-Chip Interconnects SAN JOSE, Calif, Microprocessor Forum - October 13, 2003 - MIPS Technologies, Inc. (Nasdaq: MIPS, MIPSB), today unveiled details of the highest performing 32-bit synthesizable core family within the embedded market. The disclosure of four new cores, derivatives of the recently introduced MIPS32™ 24K™ microarchitecture (see press release dated June 16, 2003), will help engineers quickly achieve their SOC design goals by offering a proven path to silicon through optimized front-to-back end methodologies and industry-standard on-chip interconnects.
MIPS Technologies also introduced a new version of its SOC-it™ system controller. Called SOC-it OCP, this version is optimized for the OCP on-chip interconnect technology developed as the native interface for all 24K cores. OCP-IP (www.ocp-ip.org) defines a high bandwidth point-to-point interconnect that addresses the performance needs of next-generation SOC designs. The SOC-it system architecture solution provides an integrated high performance memory controller (SDR and DDR) and bridging solutions to other bus standards. By coupling the SOC-it OCP with 24K cores, MIPS Technologies delivers dramatic time-to-market reductions to customers by pre-engineering the highest performance common system components.
Market Demand for High Performance, Programmability
System companies are under increasing pressure to reduce product costs while incorporating more features and functionality into next-generation SOCs. To keep ahead of this "product treadmill," engineers are turning to high performance, programmable processors to give a design more headroom so that future upgrades can be implemented in software to reduce the need to develop new silicon. The MIPS32 24K core family is ideal for these types of performance driven applications, such as integrated digital television, set-top box and DVD devices, which require high performance microprocessors to deliver an optimized user experience.
"SOC designers can use the synthesizable 24K core family to take full advantage of the highest frequency available in 32-bit cores and differentiate their products," said Mike Uhler, chief technology officer for MIPS Technologies. "To minimize the system-level design effort, we have teamed with industry-leading companies to provide customers with tailored design flows and optimized libraries, memories and bus interconnects. Furthermore, our SOC-it system controller is optimized for OCP to reduce the design requirements by providing pre-validated system level integration."
Features of the MIPS32 24K Core Family
As with all MIPS-based™ technologies, the 24K core family offers broad tool and software support only available to products based upon an industry-standard architecture. There are four 24K cores that offer a variety of configurations to support customer requirements. All cores include Release 2 features of the MIPS32 architecture that support multiprocessing, enhanced bit-field manipulation, reduced interrupt latency and enhanced cache control.
Each core is designed to serve the performance driven needs of the broadband access, office automation and digital consumer markets, and features a range of options from user extendable instructions to floating point configuration.
- 24Kc™ core: Base version incorporating an eight stage pipeline that is optimized for high performance. Includes a 32x32 Multiply/Divide Unit and configurable memory management unit with TLB or fixed mapping. Ideal for next-generation control plane applications.
- 24Kf™ core: Includes hardware floating point support that is fully compliant with the IEEE 754 standard. Floating point is a key component of several major applications.
- 24Kc and 24Kf Pro™ versions: Enabled with user extendable instructions, featuring the CorExtend™ capability. This facilitates optimization of algorithms for data-plane style processing within a programmable environment. CorExtend technology is fully compatible with the industry-standard MIPS32 architecture, so full tool chain support is maintained.
"We're going to great lengths to ensure 24K licensees will achieve 400 to 550 MHz worst case in mainstream 0.13um technologies in a small silicon foot print and within the constraints of tight development schedules," said Victor Peng, vice president of engineering for MIPS Technologies. "Companies that introduce products with more capabilities into the marketplace first have a tremendous benefit over their competitors. And we intend to give 24K licensees a significant performance and time to market advantage."
24K Core Family Support by the MIPS® Ecosystem
Cadence Design Systems
MIPS Technologies and Cadence Design Systems have collaborated to deliver a comprehensive Cadence Encounter RTL-to-GDSII reference flow for the synthesizable MIPS32 24K core family. The highly automated flow includes global synthesis, placement, routing, timing analysis and verification-providing 24K core customers with a fast, predictable path to silicon. MIPS Technologies specifically chose Cadence Encounter RTL Compiler for synthesis because of its superior quality of silicon (QOS) results.
"Quality of silicon is critical to our customers," said Jan Willis, vice president of strategic third-party programs at Cadence. "As a result of design chain collaboration with MIPS Technologies, the Cadence Encounter RTL-to-GDSII flow provides MIPS32 24K customers a rapid way to get the best silicon."
Green Hills Software
"Green Hills and MIPS Technologies are collaborating to produce a total software development solution that employs leading-edge compiler technology optimized for the 24K microarchitecture," said Christopher Smith, vice president of marketing at Green Hills Software. "Software developers appreciate our seamless solution that tightly integrates the optimizing compiler with the entire software development environment. We look forward to continuing our support for these new cores."
Mentor Graphics Corporation
"Our long-term partnership with MIPS Technologies validates our shared vision of the importance of co-verification for embedded designs, and yields high performance, accurate co-verification models of the MIPS architectures," said Serge Leef, general manager of the Mentor Graphics System-on-Chip Verification division. "The industry leading Seamless HW/SW Co-Verification solution enables designers embedding a new MIPS32 24K core to validate hardware/software interfaces in a virtual prototype prior to fabrication of the design for faster time-to-market."
MontaVista Software, Inc.
"The demanding nature of feature-rich devices not only requires high performance processors, but a robust software base that enables developers to write complex code upon a reliable operating system," said John Nielson, director of business development for MontaVista Software. "MontaVista Software has been working closely with MIPS Technologies to ensure our best-in-class technologies are tightly coupled so that SOC developers will have an optimized solution for performance-driven designs running MontaVista Linux. We applaud MIPS Technologies on their latest product advancement, and we look forward to continuing our close relationship into the future."
OCP International Partnership
"It is especially satisfying to see leading-edge technology providers such as MIPS Technologies deploying OCP and contributing to the OCP-IP Working Groups," said Ian Mackintosh, president OCP-IP. "Utilizing OCP in MIPS Technologies' 24K core family will speed time-to-market reducing risk and production costs. We are pleased to see the continuing momentum for OCP through the new product line."
Synopsys, Inc.
"Synopsys and MIPS Technologies have collaborated in the past to help ensure that SoC designers using MIPS-based cores and Synopsys' tools meet their design objectives," said Tom Ferry, vice president of marketing, Implementation Group at Synopsys. "MIPS Technologies' 24K core family enables a new level of performance which also puts new demands on the design flow. The MIPS 24K design flow is built around Synopsys' Galaxy Design Platform, which includes DC Ultra, DesignWare Library, Physical Compiler and Astro. By collaborating with MIPS Technologies, we continue to optimize our flow and help ensure that our mutual customers meet their performance targets."
Virage Logic Corporation
"Virage Logic is very pleased to be selected as an enabling memory technology for use in MIPS Technologies' new 24K product family," said Joel Rosenberg, senior director of product marketing for Virage Logic. "Utilizing the advanced high-speed, power efficient embedded memory technology in Virage Logic's ASAP Memory product line, MIPS Technologies' 24K core family delivers the highest performing processors in the industry."
Wind River Systems
"The 24K product line announcement demonstrates MIPS Technologies ability to deliver technology that is compelling to semiconductor and system companies in the digital consumer and networking markets," said Robert McCammon, director of core operating systems and tools marketing for Wind River. "By supporting the 24K product line with core Wind River technology, including the industry leading real-time operating system, VxWorks, Wind River will provide a foundation that can be extended with Wind River's market specific PLATFORM solutions for the networking and digital consumer markets, offering compelling value for OEMs and their customers."
24K™ Microarchitecture Summary
The 24K core family is based upon the recently introduced microarchitecture that offers the following technology features:
Scalable performance:
- Single issue, 8-stage pipeline
- Operating performance ranging from 400 to 550 MHz (worst case) in a 0.13 process
- Architected for scalability beyond 0.13 technology nodes
- Configurable memory management unit with TLB or fixed mapping
- 64-bit high performance memory subsystem with up to six outstanding read transactions
Implementation of the MIPS32 architecture:
- Release 2 implementation with features such as multiple general purpose register sets and support for vectored interrupts
- Reduced interrupt latency
- Code compression technology with MIPS16e™ ASE
Fits industry-standard SOC construction methodologies:
- Fully synthesizable
- Complete reference design flows for leading EDA tools
- OCP high-speed point-to-point on-chip interconnect
Optimized for market-specific implementations:
- User extendable instructions with the CorExtend capability
- Floating point support that is fully compliant with IEEE 754
- Advanced power management features
Fits low-cost requirements for embedded designs:
- Application configurability to optimize area and features
- Compact core - optimal die size
- Code size efficiency
Design time reduction:
- Maintains compatibility with the industry-standard MIPS32 architecture
- Enables access to the broad array of third party tools and software
- Leverages the extensive software investments in the MIPS32 architecture, such as middleware and application software, made by MIPS® partners during the past twenty years
Availability
MIPS32 24K cores are available to lead customers now and will be generally available for licensing in early 2004.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.
