ASIC vendors mull cost issues

ASIC vendors mull cost issues
By Ron Wilson, EE Times
October 10, 2003 (7:44 a.m. EST)
URL: http://www.eetimes.com/story/OEG20031010S0012

SAN JOSE, Calif. — A panel chaired by EE Times editor in chief Brian Fuller explored the issue of ASIC cost at the Fabless Semiconductor Association Suppliers' Expo here Thursday (Oct. 9), and came away with a mixed endorsement of recent attempts to craft new, low-cost ASIC products.

The panel was somewhat slanted in favor of ASIC vendors by the absence of one intended participant, Ivo Bolsens, vice president and CTO of Xilinx. This left Ronnie Vasishta, vice president of technical marketing at LSI Logic, Phillip LoPresti, associate vice president and general manager at NEC Electronics America and John Harrington of Agere Systems to discuss the issue amongst themselves. Unsurprisingly, Vasishta and LoPresti, both of whom have one or another form of user-configurable pre-diffused ASIC on the market, agreed that this approach could cut deeply into design cost and risk, by eliminating challenging design steps and most mask levels from the ASIC des ign.

But the conversation went deeper than just discussion of non-recurring expense. "We are living in a new world where there just aren't predictable markets for ICs," LoPresti said. "Customers are having trouble with basic product definition, and they have no visibility into customer demand. If they are going to do a design at all, they must have a low-risk, easily modified approach that commits minimal front-end investment."

After dismissing cell-based design as too expensive and challenging for many situations, and FPGAs as too expensive, slow and power-hungry, Vasishta said that in many cases Platform ASICs, as LSI calls its RapidChip product line, are here to stay. "We think that cell-based design will stay, too," he said. "But it will only be used in cases where you get a real differential advantage in the end product by doing all that work."

But Harrington expressed caution about the structured ASIC approach. "We have experimented with ideas like this for years at Agere," he said. "In our markets — communications infrastructure, consumer and storage, among others — price is the first four things customers look for. We offered them the front-end savings of structured parts, but they always needed a little more RAM, or a few more I/Os, or some other adjustment. The structured part always turned out to be the start of the conversation rather than the solution to the problem."

Asked if that would be the case again, or if structured ASICs were really gaining traction, LoPresti turned to numbers. "Since April 2002 we have done 30 structured designs," he said. "And there are many more design teams looking at the approach, waiting for demand to materialize."