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Toshiba devises way to develop IC hardware, software in parallel
Toshiba devises way to develop IC hardware, software in parallel Having reduced chip development time with its SoCMosaic platform, Toshiba Corp. is now attempting to further shorten time-to-market for custom chips by introducing today a design method to let hardware and software development take place in parallel. Consisting of a programming and debugging environment, emulation system, and co-verification tools, the approach can cut six months to a year off software development, according to Toshiba. This, combined with a shorter chip development cycle--about eight months from concept to silicon--is a powerful alternative to structured-ASIC approaches, the company claims. Structured-ASIC suppliers also profess to slash development time, but they force customers to make design compromises and don't save much cost in the long run, according to Richard Tobias, vice president of the ASIC and foundry business at Toshiba America Electronic Components Inc. in San Jose. "The NREs for structured arrays are less by a couple hundred thousand dollars, but the engineering time and cost will be similar to any other type of ASIC approach," Tobias said. "With SoCMosaic you still pay the full mask cost, but we've reduced the risk and shortened the cycle so much that it makes up for the slightly more expensive masks." SoCMosaic is a soft-IP approach that relies heavily on FPGAs and fast I/Os in an emulation environment. Sonics Inc.'s Open Core Protocol-based IP backplane acts as the on-chip bus. The custom-chip platform is offered for 0.18- and 0.13-micron designs in any volume that makes cost sense, but generally starting at 20,000 units a year, Tobias said. Ordinarily, a customer can't start software development until the custom chip comes back from the fab. Toshiba said its combined hardware/software environment allows software development to begin within a day of the SoC's concept being defined. Based on the customer's definition, Toshiba provides an RTL model that can be plugged into its hardware/software co-development environment. The environment allows programmers to work with a variety of SoC simulation modes while preserving the same programming interface from start to finish. Toshiba said this approach can uncover bugs earlier that might have resulted in costly silicon re-spins. The emulation platform is provided by WhiteEagle Systems Technology, and comes with customizable I/O cards, design automation tools, and host application software. Toshiba has also tapped Mentor Graphics Corp. for a co-verification environment that links software development and debug tools with logic simulation to deliver co-verification before hardware prototypes are ready. Toshiba's development environment is available for a license fee that varies depending on complexity of the project. The Mentor and WhiteEagle products are available from their respective vendors.
Copyright 2004 © CMP Media, LLC
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