SoC panel ponders process node tradeoffs

SoC panel ponders process node tradeoffs
By Michael Santarini, EE Times
October 15, 2003 (10:12 a.m. EST)
URL: http://www.eetimes.com/story/OEG20031015S0022

SAN JOSE, Calif. — Chip companies must consider platforms, performance, area, power, mask costs and time-to-market risks when implementing their designs in a given process technology, according to industry panelists at the SoC Online Conference.

Francois Gregoire, vice president of technology at Altera Corp., based here, said process migration, once a relatively simple task, has at 90 nm become quite complex. Considerations include the use of low-k dielectrics, multiple process parameters affecting performance and standby power, which is becoming an increasing portion of the power budget for a design.

"As a result adoption [of 90 nm] lags three years behind 130 nanometers," said Gregoire.

Gregoire said the situation will become even more complex at 65 nm as leakage current keeps rising and interconnect scaling worsens. Since there is no replacement for 193-nm steppers, lithography at 65 nm also becomes very problematic, he added.

Hi saya Keida, general manager of the product marketing and development department at Kawasaki Microelectronics, said reticle costs doubled in the transition from 150 nm to 130 nm and may doubled again at the 90-nm process node. At the same time, wafer costs have more than doubled at 130 nm and even higher at 90nm.

These concerns mean users must pick the right technology to fit their design volume and size. A serious consideration, said Keida, is using FPGAs rather than ASICs.

"But as gate counts increase, the price per gate of FPGAs is much much higher than ASICs," noted Keida.

Hence, Keida concluded that FPGAs are a good choice if designers are targeting designs in the 250,000- to 500,000-gate range. He also said implementing ASICs in 250- and 180-nm processes provide better costs and flexibility than FPGAs, with the extra advantage of requiring less power.

Ronnie Vasishta, LSI Logic's vice president of technology, said several companies are now offering an alternative to standard ASICs and F PGAs: structured or platform ASICs targeted specifically for those who need to quickly enter volume production.

"Platform ASICs have come in to address the new challenges and technology complexities," said Vasishta. "We will see many more design starts in platform ASICs at 90 nm than cell-based ASICs. People will be able to utilize the design methodology and process methodology."

Kevin Kolwicz, director of technology strategy at Agere Systems, said that when selecting a process, Agere bases its decision on the availability of key IP as well as the skill sets of its designers. The company also weighs product requirements versus technology readiness for given design projects. He said the company uses other criteria when designing standard products versus ASICs.

Riko Rakojcic, director of design at PDF Solutions, said a thorough tradeoff analysis involves considering performance, price and risk before picking a process for a given project. "The thing to do is to focus on managing risks," said Rakojc ic. "If you implement a methodology to deal with design for manufacturability or statistical design, then you manage risks offline. It makes it so the decision on process technology can be driven be sheer price-performance tradeoffs."

The full panel discussion can be viewed at www.soconline.com.