eASIC Introduces a Maskless Customization Approach for No-NRE Structured ASIC

San Jose, California, January 27, 2004 -- eASIC Corporation, a provider of configurable Structured ASIC technology, today introduced a maskless customization approach aimed at eliminating NRE (non recurring engineering) cost for ASIC. The NRE and mask-set cost are removed since eASIC employs direct-write e-Beam approach rather than conventional mask lithography for IC customization. Due to the company’s innovative Via-customization technique, eASIC’s fabric yields about 10 times higher throughput from Direct-write e-Beam machines, compared to metal customization. This is made possible as Vias occupy about 1% area of the customization layer, while metal occupies at least 30%, thus reducing the time e-Beam machine needs to spend writing the customization. Moreover, only a single Via-layer is required for Structured eASIC customization, which further shortens the turnaround time and eventually cuts the cost.

“The lengthy time to design a cell-based ASIC has likely impacted the number of new chips even more than the much-publicized multi-million dollar expense,” said Jordan Selburn, Semiconductor Analyst with iSuppli Corporation. “Techniques such as direct-write e-Beam can dramatically reduce this time-to-design by allowing engineers to explore multiple design iterations in parallel rather than the current cumbersome and inefficient parallel approach.”

eASIC is the only company that can offer ASIC without NRE cost. Although FPGAs do not require NRE either, their per-unit cost is significantly higher than ASIC’s and their performance is lower by about an order of magnitude. Using e-Beam for Structured eASIC customization is a preferred alternative for prototyping and low volume. For higher volumes, a single Via-mask can be used for the routing customization. The logic in both options (i.e. e-Beam and Via-mask) is customized with bit-stream and Look-Up-Table (LUT), similar to FPGAs, providing flexibility and ease-of-design, in addition to the low cost and high performance.

The Structured eASIC customization technology was designed to work with existing Direct-write e-Beam machines from vendors like Leica or Advantest. This type of Direct-write e-Beam machines for semiconductor customization is available at numerous foundries and ASIC service providers such as ST Microelectronics, UMC and Fujitsu. eASIC’s maskless technology was successfully tested and implemented in silicon at 0.13 micron by a large IDM (Integrated Device Manufacturer) customer.

“eASIC’s technology makes the maskless lithography feasible today, suitable for currently available equipment that enables Zero-NRE ASIC and removes the high-cost barrier for design starts”, said Zvi Or-Bach, eASIC President and CEO. “Before the product matures for high volume production, the use of Structured eASIC with Direct-write e-Beam is very cost effective. Moreover, since with eASIC fabric the logic is programmed by bit-stream, it allows for a very easy post-fabrication debug and short time-to-market. As the product matures for high-volume and may need migration to Standard Cell, using Structured eASIC is followed by one NRE payment, while other Structured ASIC solutions end up with double NRE charge: one for structured ASIC and one for Standard Cell. I believe maskless lithography marks an important leap forward for semiconductor economics in today’s deep-submicron reality”.

About eASIC

eASIC® has developed a breakthrough Structured ASIC technology aimed at dramatically reducing the overall fabrication cost and time of customized high performance semiconductor chips, efficiently utilizing standard manufacturing processes. By innovative use of proven logic programming together with efficient metal routing, eASIC’s technology enables rapid and low-cost ASIC design, as well as cost-effective customization of System-on-Chip and platform-based designs. With its unique technology, which was successfully proven in silicon and validated by customers, the company is positioned to become the preferred ASIC solution, targeting the emerging Structured ASIC market, which is defined as the gap between FPGA and Standard Cell.
eASIC Corporation is a privately held company, founded In 1999 by Zvi Or-Bach, the founder of Chip Express. Headquartered in San-Jose California, eASIC holds a highly skilled and motivated engineering and R&D team in Romania.