Faraday Sets the Stage for Structured ASIC Technology Benchmarking

Technology leader unveils benchmark suite for industry-wide use in comparing Structured ASIC technologies; publishes its own results for anyone to challenge

SUNNYVALE, California, and HSINCHU, Taiwan – February 2, 2004 - Faraday Technology Corporation (TAIEX: 3035), a leading fabless ASIC and IP provider, today announced that it has created a benchmark suite for IC designers to compare its Structured ASIC technology against other vendors'. The company formally announced the Structured ASIC Benchmark at DesignCon 2004; all the test cases and Faraday's benchmark test results are also available at its Web site.

"Soon after Faraday unveiled its Structured ASIC – Metal Programmable Cell Array (MPCA) technology last year, we realized that IC companies really needed realistic benchmarks that they could readily use to compare and make critical decisions about how to adopt the new technology," said Hsin Wang, Senior Technical Director of Faraday Technology Corp. "Some vendors did provide benchmarks to selected customers, but most of the test cases they chose were either too small, artificial, or not well enough documented to be used across different technologies. We have chosen to release a benchmark suite that makes it easy for everyone to compare various Structured ASIC technologies," added Hsin Wang.

For these benchmark test cases, Faraday has chosen three of the most typical applications for Structured ASIC: a 16-bit general purpose DSP, a 32-bit RISC processor, and a bus controller with DMA engine. Each of the three test cases is a complete design database which had been used dozens of times by Faraday's customers, using well accepted Verilog coding style. The test cases come complete with synthesis and verification scripts, but to protect these intellectual properties, Faraday has scrambled the names and inserted some functional errors into the designs.

“Comparing the different design technologies that comprise the rapidly evolving Structured ASIC market segment can be very confusing to designers looking to accelerate the design time and lower the cost of system-on-a-chip (SoC) designs,” noted Jim Lipman, President of SemiView, an industry consulting firm focused on Application Adaptable ICs (AAICs). “Faraday has taken a significant first step in Structured ASIC evaluation with its creation of a benchmark suite of three real-world applications. SemiView looks forward to being an active participant in bringing together other vendors with Faraday for expanding these and other benchmark circuits across several Structured ASIC technologies.”

Faraday also provides performance reports based on actual cases, a rare move further demonstrating the company's confidence in its technology and its commitment to this market. Faraday has openly published its Structured ASIC benchmark results using its 0.13um MPCA library on its Web site, and welcomes all to verify them.

"In comparison to typical standard cell libraries, we expect to be within less than a 15% loss in performance, and seldom more than a 35% increase in area -- results that we believe will rank us as one of the best Structured ASIC technology providers," said Hsin Wang of Faraday. "Moreover, the logic of Structured ASIC is 10 times denser than in an FPGA, and performs 10 times faster. In other words, Faraday's MPCA library delivers performance and density much like that of standard cells, with all the benefits of FPGAs and gate arrays including dramatically reduced NRE, shorter wafer processing time and most important, fast time-to-market," he added.

Availability
Faraday formally announced the Structured ASIC Benchmark at DesignCon 2004 at the Santa Clara Convention Center, February 2-5. Customers, prospects (and even competitors) can download the RTL synthesis script from Faraday's Web site and compare the results against other Structured ASIC libraries. Faraday is also putting a complete version of its benchmark results on its Web site for anyone in the world to challenge.

The Structured ASIC Benchmark Web address is:
http://www.faraday-tech.com/StructuredASIC

Table 1: Test results summary

Test Case 16-bit DSP 32-bit RISC CPU DMA Controller Methodology MPCA Standard Cell MPCA Standard Cell MPCA Standard Cell Gate Count 127K (excluding memories) 260K (excluding memories) 60K Routing Metal Layers 3,4,5 1,2,3,4,5 3,4,5 1,2,3,4,5 3,4,5 1,2,3,4,5 Cell area/ Total area 95.3% 96.69% 91.3% 90.83% 80.0% 94.3% Block Area (um2) 950x950 (including memories) 790x790 (including memories) 1490x1490 1200x1200 680x680 510x510 Memory Sizes 32x12 (35853 um2) 32x26 (54433 um2) 512x32 (82739.2 um2) x4 128x22 (34733.76 um2) x2 8x32 (18046.56 um2) x1 Not Applicable Post-Layout Timing* 10.9 ns 9.98 ns 6.56 ns 6.21 ns 7.51 ns 6.93 ns

* Worst process corner, 1.08V, 125°C

About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, DSPs, PHY/Controllers for USB 2.0, Ethernet, and Serial ATA. With more than 500 employees and 2003 revenue of $111 million, Faraday is the largest fabless ASIC company in all Asia-Pacific. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: http://www.faraday-tech.com