De Geus noted that the average complex system-on-chip (SoC) today consists of approximately 50% memory by area. The International Technology Roadmap for Semiconductors (ITRS) predicts that this will grow to over 90% by 2011. "This means that memory will have a dominant impact on chip cost, area, power, and yield," De Geus said. MoSys' 1T-SRAM technology provides significant savings in each of these areas, he claimed. De Geus noted that MoSys achieved about $19 million in revenue in 2003, with a small sales force and no other IP. "Many potential customers were reluctant to do business around such a crucial technology with what they perceived to be a fairly small company," he said. "The combination of MoSys' technology and Synopsys' sales/distribution/support channel, plus links to our DesignWare IP portfolio, should provide the ability to deliver great value to our customers and translate into significant sales for Synopsys."
Responding to a question about leakage current at 90 nm, De Geus noted that MoSys' 1T-SRAM addresses this issue. "1T-SRAM is actually a dynamic bit cell at its heart (one transistor and capacitor) with no connections across the power rails," he said. "So, unlike traditional 6T-SRAM architectures, the MoSys 1T-STAM memory is really not faced with the same leakage issues as 6T cells. MoSys has measured the leakage of their 1T-SRAM memories in 'retentive standby mode' to be about 25% of comparably sized 6T memories."
Responding to other questions, De Geus said Synopsys is not relying on acquisitions for all of its technology development. He said that about 25% of Synopsys revenue is invested in R&D, and mentioned internally-developed technology such as Magellan, the constraint solver technology in Vera, the assertion technologies in VCS, signal integrity-related capabilities in PrimeTime, and logic built-in self test (BIST).
De Geus said that Synopsys employs around 300 engineers overseas and more than 1,000 in the U.S. He said that centers in India, Taiwan, China, Germany, France, Ireland, Canada, and Korea allow Synopsys to be "globally competitive."
Asked about structured ASICs, De Geus said "the jury is still out" as to whether the business model will work. He acknowledged that ASIC design starts are down, but noted that the size of the designs has "gone up tremendously, fueling growth in the EDA tool market." He also noted that complex FPGAs are beginning to require "ASIC strength" tools and flows.
De Geus also provided a detailed list of Synopsys products available under Linux on AMD Opteron and Intel Itanium 2 platforms.
Asked about Synopsys' recent decision to "end of life" Behavioral Compiler and SystemC Compiler, De Geus responded that "we found that most customers were either not willing to take the QoR (quality of results) hit necessary to use these products, or they were not willing to complicate their verification flow." But he noted that some technology from Behavioral Compiler was folded into Design Compiler.
De Geus also denied statements that Synopsys is abandoning SystemC. "Actually, we have increased our investment in SystemC integration in the verification flow, with the integration of System Studio with RTL verification," he said.
De Geus returned often to what has become a favorite theme — silicon IP. "The 65nm chip in 2007 that is on the roadmap will have 31 million gates of reused logic, a similar amount of new logic, and over 30 megabytes of memory," he said. "Looking at these numbers clarifies why Synopsys is putting so much emphasis on assembling a very high-quality IP portfolio."
