| SAN JOSE, Calif. — Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) next week will unveil a revamped business strategy meant to take on the increasingly difficult task of designing, manufacturing and testing advanced semiconductor devices. At the same time, the company will announce that it has manufactured its first 65-nanometer test chip. TSMC's "platform" approach, which will be announced at the company's technology symposium here next Tuesday (Aril 13), is meant to address the disconnect between chip design and manufacturing, which has worsened in recent years with the shift to 130- and 90-nm process design rules. The gap has been pegged as a root cause for fundamental changes that are reshaping the semiconductor industry, from a decline in the number of full-custom chips being designed to the scarcity of venture capital funding for startup chip companies. At past symposia, TSMC has weaved in suggestions about how to address design-to-manufacturing problems within the framework of discussion about process technology. This year, design-for-manufacturing will be a central theme. "What we have done is positioned our technology and design services into a holistic approach that we call platforms," said Chuck Byers, director of brand management at TSMC. "Success is going to depend on something more than process technologies. What is required is an integrated environment for the backend, assembly, test, packaging and libraries. All that needs to be addressed up front." The company said it has tweaked its marketing focus accordingly, appointing two senior managers to lead the platform effort. Ken Chen, who was overseeing business development for TSMC in Japan, is now director of mainstream technology platform marketing. John Wei, the former director of Fab 5 in Hsinchu, Taiwan, has been reassigned to director of advanced platform marketing. As part of the plan, TSMC will present a new set of design guidelines for its most advanced process technologies, particularly for 0.13-micron and below. Some of the these structured design rules "are absolutely required to achieve certain yields; others are suggested for certain yields," Byers said. The platform design strategy is being rolled out as the company prepares to disclose plans to fabricate chips based on 0.065-micron design rules. Next week, the company will announce that it has produced its first 0.065-micron SRAM module and that it plans to start making the first low-power devices at that process node by late 2005. The high speed version will be ready in the first half of 2006, followed by the general purpose process module in the fourth quarter, Byers said. The company's most advanced chips today are based 90-nm design rules, which is slated to move into full production by the second half of this year. At the symposium, the company will also discuss technical details for its "half node" 0.11-micron process technology and new ways to support older nodes starting at 0.18-micron and greater, Byers said. In order to succeed, TSMC is seeking more backing from third-party companies, including those developing software tools and intellectual property cores. Emphasizing this point, Synopsys chief executive officer Aart de Geus will deliver a keynote stressing the importance of moving to a more collaborative design model, Byers said. | 
