TransEDA Again Accelerates System-On-Chip Verification with New Version of its Verification Navigator Environment

TransEDA Again Accelerates System-On-Chip Verification with New Version of its Verification Navigator Environment

New 2002.1 Version Features Dozens of Enhancements
Including Exclusive FSM Path Coverage and Dual-Language HDL Checking
 

Los Gatos, Calif. - January 21, 2002 - TransEDA® PLC, the leader in ready-to-use verification solutions, announced a new version of its Verification Navigator® Integrated Design Verification Environment. The product features significant enhancements to the VN-Check[tm] Configurable HDL Checker, the VN-Cover[tm] Coverage Analysis solution, and the VN-Control[tm] Application-Specific Test Automation solution.

New Features in VN-Check for Configurable HDL Checking
VN-Check is a configurable HDL checker that lets users organize checks into rule sets. This supports fast, targeted analysis of specific design characteristics such as finite state machines (FSMs), design-for-test, or design-for-reuse. VN-Check now includes mixed Verilog and VHDL dual language support, Verilog IEEE 1364-2001 language support, and enhanced run-time and memory performance. In addition, VN-Check now includes the VN-Check CRC custom rule creation option in the base configuration. This option was previously available only as a separately priced product.

 "Many of today's designs have dual language requirements," said Tom Borgstrom, vice president of marketing at TransEDA. "Our goal with new dual-language support is to let our customers focus on capturing a design, and rely on VN-Check to analyze the design to catch serious bugs in their code before simulation."

 Added Functionality in VN-Cover, the Industry-leading Coverage Analysis Tool VN-Cover is the industry-leading coverage analysis solution with comprehensive code, FSM, and functional coverage for Verilog, VHDL and dual-language designs. VN-Cover 2002.1 features a new, exclusive FSM path metric as well as support for 64-bit simulation platforms.

 VN-Cover's new FSM path coverage metric accelerates verification and analysis of complex control blocks based on finite state machines. VN-Cover automatically extracts and analyzes FSMs in a design, abstracting their functionality in terms of "cycles," "supercylces" and "links." This sophisticated analysis capability-unique to VN-Cover-enables coverage of the abstracted FSM behavior to be measured during simulation, which ensures that critical control functionality is well verified. By automatically abstracting FSM functionality, VN-Cover can provide a much more meaningful picture of the quality of verification with little additional effort from the user.

 "Finite state machines are often key elements of complex designs, so it makes sense to pay extra attention to them during verification," Borgstrom said. "FSM path coverage complements code coverage by providing a higher correlation with the design's functionality."

 VN-Cover 2002.1 is also the first and only full-featured coverage analysis solution for Model Technology's 64-bit simulator. Many design teams are migrating towards 64-bit hardware platforms for verification to take advantage of the higher memory capacity required for large SoC designs.

 "Model Technology's ModelSim® simulator leads the industry with full 64-bit support on the greatest number of hardware platforms," said Dennis Brophy, director of strategic business development at Model Technology. "TransEDA's support for 64-bit versions of ModelSim will enable our customers to achieve coverage closure on even the largest designs."

 New VN-Control Now Fully Integrated into Verification Navigator
VN-Control is an application-specific test automation solution that works with TransEDA's Foundation Models Verification IP to enable ready-to-use automatic test generation and results checking from a high-level test template. VN-Control 2002.1 is fully integrated into the Verification Navigator environment.

 "The integration of VN-Control into the Verification Navigator environment furthers our goal of providing a single, unified environment with multiple best-in-class verification tools," Borgstrom said. "Once a designer is familiar with a tool in the environment, it will be easy for him or her to take advantage of other tools provided, eliminating worries about tool-interoperability issues."

 About Verification Navigator
Verification Navigator is an integrated design verification environment providing a suite of tools that enable HDL designers to manage and shorten the verification process. Verification Navigator is comprised of VN-Control[tm], VN-Check[tm], and VN-Cover[tm], as well as the VN-Optimize[tm] test suite analysis solution. VN-Optimize reduces regression test time by identifying the shortest set of tests that achieve the target verification goals.

 Verification Navigator supports all leading Verilog, VHDL, and dual-language simulation environments including Cadence Affirma, NC-Verilog, NC-VHDL, NC-Sim, and Verilog-XL; Model Technology ModelSim Verilog, ModelSim VHDL, and ModelSim SE; and Synopsys VCS and Scirocco. Verification Navigator is available on Solaris, HPUX, AIX, Linux, Windows NT, and Windows 2000 platforms.

 About TransEDA
TransEDA PLC (symbol TRA on the Alternative Investment Market in London) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models for advanced microprocessors and bus interfaces.

 TransEDA's design verification software performs application-specific test automation, configurable HDL checking, functional, finite state machine (FSM) and code coverage analysis, and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the world's top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, Calif. 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, email: info@transeda.com.

 Note: TransEDA and Verification Navigator are registered trademarks and VN-Check, VN-Cover, VN-Control, VN-Optimize, Simulation Edge and Foundation Models are trademarks of TransEDA. All other trademarks are properties of their respective holders.
 

MEDIA CONTACTS:

 In North America, Asia, and Japan:
TransEDATom Borgstrom
408.335.1303
tom.borgstrom@transeda.com

 Armstrong Kendall, Inc.
Jen Bernier
408.975.9863
jen@akipr.com