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EDA startup enables virtual IC prototypes
EDA startup enables virtual IC prototypes OTTAWA Seeking to provide a "virtual prototype" early in the silicon design process, EDA startup Icinergy Software announced its SoCarchitect design planning product this week. The company is a spin-off of EDAConnect.com, an online provider of EDA tools. Icinergy, based here, promises that SoCarchitect will capture physical chip design attributes before RTL coding begins. It creates a high-level floor plan and provides estimates of timing, power, area and routability. The hierarchical floor plan can then be refined as designers synthesize and lay out individual blocks. SoCarchitect may seem like unusual technology to come from EDAConnect.com, which mostly resells other vendors' pc-board layout tools, but the product has been brewing for years. The seeds of Icinergy were planted in 1999 when EDAConnect.com purchased Javelin EDA, an Ottawa startup developing automatic placement technology for ICs and p c-boards. EDAConnect.com released a pc-board floor planner based on Javelin technology, and customers were asking the group to develop an IC design planning product, said Scott McLellan, the former president and chief executive officer of Javelin, who now holds those positions with Icinergy. Once work on the IC product was completed, the group added a few people and took steps to spin-out as Icinergy. "We were doing different things, and we felt it was in the best interests of the company [EDAConnect.com] to split into two distinct pieces," said McLellan. John Cooper, the EDA icon who co-founded Cooper & Chyan Technology Inc. (CCT), is chairman of the board of both Icinergy and EDAConnect.com. He is also Icinergy's majority shareholder. Even so, McLellan said Icinergy is "completely independent" from EDAConnect.com. Before his stint with Javelin, McLellan was president and CEO of Unicad, a pc-board analysis company acquired by CCT prior to CCT's purchase by Cadence Design Systems Inc. Like most o f Icinergy's eight employees, McLellan also once worked at Ottawa-based Nortel. Early picture SoCarchitect is a hierarchical design planning tool that promises to capture a designer's intent at a very high level of abstraction. "This is pre-RTL planning," said McLellan. "You can take IP [intellectual property] from a variety of sources, whether it's a soft block in Verilog or a hard block in GDSII, and put it together to form a picture of the chip." This early picture, said McLellan, can help chip designers meet timing constraints, avoid routing congestion, and optimize ports. "With hierarchy, we can bring all the pieces together when they get more detail and continually optimize," McLellan said. For a final view, he noted, designers can import LEF and DEF layout files. In addition to inputting Verilog, GDSII, LEF or DEF, designers can create blocks "on the fly" by describing attributes such as gate count, power per gate, and aspect ratio, Icinergy said. Floor planning can be total ly interactive or semi-automatic, and a fully automatic floor planning capability is "very close," McLellan said. The tool can reshape the aspect ratios of soft blocks and optimize ports automatically as it does placement, the company said. Icinergy is not claiming to offer a top-level router, but SoCarchitect does a "practical routing implementation" to help it make timing, area and power estimates, McLellan said. These estimates, he claimed, are typically within 10 percent of actual values. SoCarchitect can provide constraint data to feed RTL synthesis tools, or physical data for gate-level floor planners. It doesn't offer full-scale HDL code generation, but McLellan said it can automate the "really boring part of Verilog" by generating wire definitions, module instantiations and connectivity. SoCarchitect is shipping now, and Icinergy claims to already have customers, although McLellan declined to name any. The product starts at $35,000 for a standard node-locked license, and will also be avai lable on a short-term basis through EDAConnect.com's EDA Store. It runs on Solaris and Windows platforms.
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