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Magma Announces Support for Virage Logic Structured ASIC Design Libraries
SANTA CLARA, Calif., April 26, 2004 – Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design solutions, and Virage Logic Corp. (Nasdaq: VIRL), a leading provider of best-in-class semiconductor IP platforms, today announced their joint collaboration has produced a design flow that works for both structured-ASIC and standard cell libraries. Magma’s Blast Fusion® support for Virage Logic’s Area, Speed and Power (ASAP) Logic™ Metal Programmable Libraries has been validated by both companies and will be added to existing support for the ASAP Logic Standard Cell Libraries. This will enable mutual customers to make trade-offs between density, cost and performance according to their requirements. Customers will be able to use Magma’s standard ASIC design flow and Virage Logic’s libraries that include all the necessary requirements and constraints for their structured ASIC designs.
“Virage Logic’s approach to structured-ASIC design is unique in that it allows semiconductor vendors to design and create structured-ASIC platforms that are specific to their market requirements,” said Behrooz Zahiri, director of product marketing at Magma. “We’re very pleased to expand our partnership with Virage Logic to enable our mutual customers to employ an integrated RTL-to-GDSII design flow for structured ASIC designs that offers low-cost manufacturing, fast turnaround, and performance and density results that are close to those of standard cell ASIC designs. And, for our customers that use a COT flow, we can now offer a structured ASIC design flow with complete control from RTL to GDSII.” “Working closely with Magma to support our ASAP Logic Metal Programmable Libraries provides our mutual customers with the added benefit of cutting costs and reducing turnaround time with mask generation in their structured-ASIC design flow,” said Brani Buric, senior director of product marketing at Virage Logic. “Magma users now have the flexibility of mixing and matching our metal programmable and standard cell libraries on the same design to achieve maximum savings in overall chip costs.” About Magma’s Structured-ASIC Design Flow Magma’s structured-ASIC design flow is based on the company’s existing ASIC design flow. This makes it extremely easy for current Magma users to adopt because it uses the same GUI, design and analysis engines, and data model architecture. Magma’s unified data model and the newly deployed architecture-specific mapping and physical design deliver structured ASICs with higher quality of results, predictable performance and faster timing closure. About Virage Logic’s ASAP Logic Cell Libraries The ASAP Logic Metal Programmable Cell Libraries significantly reduce overall mask costs by allowing minimum changes in masks to achieve any necessary product revisions or personalization of the chip. Performance and area are competitive with standard cell products currently in the marketplace. The ASAP Logic Standard Cell Libraries feature up to a 30 percent reduction in logic area resulting in at least a 10 percent cost reduction. ASAP Logic Standard Cell Libraries achieve the same or better performance than conventional cell libraries and also feature lower power consumption. Availability For Magma library view availability, please contact Virage Logic. About Virage Logic Virage Logic Corp. (Nasdaq: VIRL) is a leading provider of best-in-class semiconductor IP platforms based on memory, logic, and I/Os that are silicon proven and production ready. Virage Logic meets market demands for cost reduction, while improving performance and reliability for fabless and integrated device manufacturer (IDM) companies focused on the consumer, communications and networking, handheld and portable, and computer and graphics markets. Virage Logic is headquartered in Fremont, California and has sales and support offices worldwide. For more information, visit www.viragelogic.com or call (877) 360-6690 toll free or (510) 360-8000. About Magma Magma provides leading software for designing highly complex integrated circuits while maximizing Quality of Results with respect to area, timing and power, and at the same time reducing overall design cycles and costs. Magma provides a complete RTL-to-GDSII design flow that includes prototyping, design planning, synthesis, place & route, and signal and power integrity chip design capabilities in a single executable, offering “The Fastest Path from RTL to Silicon”™. Magma's software also includes products for advanced physical synthesis and architecture development tools for programmable logic devices (PLDs); capacitance extraction; and characterization and modeling. The company’s stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com. # # # Magma and Blast Fusion are registered trademarks and “The Fastest Path from RTL to Silicon” is a trademark of Magma Design Automation Inc. All other product and company names are trademarks or registered trademarks of their respective companies. FORWARD-LOOKING STATEMENTS: Except for the historical information contained herein, the matters set forth in this press release, including statements about the features and benefits of Virage Logic’s and Magma’s solutions, are forward-looking statements within the meaning of the "safe harbor" provisions of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially including, but not limited to the ability of Magma’s and Virage Logic’s products to produce the desired results and Magma’s and Virage Logic’s abilities to keep pace with rapidly changing technology. Further discussion of these and other potential risk factors may be found in the parties' latest filings with the Securities and Exchange Commission on form 10-K, and any subsequent updates thereto on form10-Q. These forward-looking statements speak only as of the date hereof. The parties disclaim any obligation to update these forward-looking statements. Virage Logic’s Safe Harbor Statement under the Private Securities Litigation Reform Act of 1995: Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic’s ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic’s ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic’s ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic’s technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company’s ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company’s ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company’s Annual Report on Form 10-K for the period ended September 30, 2003, and in Virage Logic’s other periodic reports filed with the SEC, all of which are available from Virage Logic’s website (www.viragelogic.com) or from the SEC’s website (www.sec.gov), and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.
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