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Toshiba Will Apply Sarnoff's TakeCharge IC Design Approach To Chip Processes Down To 65 NanometerNew Agreement Extends Toshiba/Sarnoff Strategic Cooperation; TakeCharge Solutions Already Proven In Toshiba Processes As Small As 90nm Princeton, New Jersey and Tokyo (May 13, 2004) -- Sarnoff Corporation (www.sarnoff.com) and Toshiba Corporation of Tokyo, Japan (www.toshiba.com) today announced that Toshiba will implement the TakeCharge® on-chip electrostatic discharge (ESD) design approach from Sarnoff in its CMOS integrated circuit processes (0.18um, 0.13um, 90nm and 65nm process technology). As part of the agreement, Sarnoff will also collaborate with Toshiba in order to develop customized solutions for future generations of Toshiba ICs in geometries as small as 45nm and 32nm. “TakeCharge technology helps us reduce the die size of our chips for greater economy, while maintaining and ensuring ESD protection in all application areas including high speed,” said Shigeo Koguchi, President and CEO of Toshiba’s Semiconductor Company. The new strategic agreement between Toshiba and Sarnoff extends a relationship that began in 2000. TakeCharge technology has already been silicon-proven in Toshiba’s CMOS products with advanced process technologies of 0.18um, 0.13um, and 90nm, and is currently being verified in 65nm. “We’ve had consistent success in designing more compact, higher-performance ESD protection into our ICs with TakeCharge,” said Naoyuki Shigyo, Chief Specialist, System LSI Design Department, Toshiba’s Semiconductor Company. “We will continue to collaborate with Sarnoff to develop solutions for our future processes such as 45nm and 32nm.” TakeCharge has been used successfully in high-volume 0.18um CMOS and 0.13um CMOS ICs starting in 2002, and is currently being implemented in the first 90nm CMOS products. “We are proud to be working with Toshiba’s Semiconductor Company, one of the world’s premier sources of IC innovations,” said Koen Verhaege, Director of ESD Design Solutions & Executive Director of Sarnoff Europe. “The effectiveness of TakeCharge has been demonstrated at leading foundries in Japan and around the world. But this agreement with an industry leader based on extensive experience with the technology is especially gratifying.” In addition to significant die size reductions, TakeCharge technology ensures “first time right” ESD design, according to Verhaege. With more dies on a wafer and less time spent in (re)design, the technology has the potential to save millions of dollars in product development and production costs. It also helps eliminate the cost of additional mask sets. About Toshiba About Sarnoff About Sarnoff Europe
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