| SAN JOSE, Calif. — The semiconductor intellectional property market is fraught with problems but also with opportunities, a panel of experts said during the Semiconductor Venture Fair here this week. The panel included tool and IP vendors, IP users, analysts and an investor. Opinions varied widely on the state of the IP business. Vin Ratford, president of design estimation vendor Giga Scale IC, warned that chips have become too complex and that crucial data about the design is available too late in the cycle. He said IP vendors face the validation of designs across a huge number of variations. "There are 11 process variants, about 30 libraries and over 100 memory compilers available just for [foundry Taiwan Semiconductor Manufacturing Co. Ltd.],'' he warned. Not enough SoC designs are getting through the design flow and into production, he added. "But problems mean opportunities,'' Ratford said. "In the last two years there have been 52 EDA startups. There will be 40 new exhibitors at [the Design Automation Conference] this year." Rich Wawrzyniak, senior analyst at Semico Research, offered additional hope. "We used to look for a killer ap," Wawrzyniak said. "But today, you don't find one killer ap. You find clusters of smaller, fast-moving applications in areas like consumer electronics. They are only good so long as the end product is trendy. The only way to respond quickly enough to catch these markets is heavy use of IP." Kurt Wolf, director of library management at TSMC, said "IP use is still a conversation between user and supplier. It's much like the relationship between a venture capitalist and an entrepreneur, only when you have due diligence by the user and a tight focus on quality by the provider you get growth." Wolf said TSMC's role is providing silicon validation, the ability to merge GDS-II-level IP at the foundry to prevent theft, mediation between provider and user and feedback for prospective users on manufacturability and user experiences with specific IP. Liam Goudge, director of business development at ARM Ltd., added that "ARM spends about $45 million a year just to stay on the CPU design treadmill. The time-to-revenue on a new CPU core is about five years." Mark Templeton, president and CEO of Artisan Components, offered the view from a library developer. "In board-level design, ICs are black boxes," he said. "The interfaces and behaviors of ICs are specified in data sheets so well that no one needs to know what goes on inside them. Chip design has to get to that same level-we have to be able to drop a block into a chip design without knowing what's inside it. And we need more choice. A chip designer today has few choices in IP. But a board designer has tens of thousands of chips to choose from." Aurangzeb Khan, vice president of business development and CTO at Cadence's design services operation, underlined the need for IP and reuse skills. "The life cycle of a chip in consumer electronics today is about nine months," he said. "Typically, you have to go from engineering samples to full production in three months. So if you have even a metal mask turn, you will miss the market. The quality of the IP you use and the quality of the design chain that integrates it are both vital-there is no second-time success." Khan said IP designers had to have the perspective of their users and of the end market. "Open collaboration across design and supply chains is critical," he warned. Lucio Lanza, managing partner of Lanza Technology Ventures, offered the venture capitalist' perspective. "IP is a bad investment. That's obvious," Lanza said. "Almost all of the successful IP companies are represented right here at this table." Lanza then listed three categories of IP: architectural, physical and standard-compliant IP. A fourth type, snthesizable IP, by itself lacks staying power in the market, he added. Once its function was understood, price competition would end its profitability. "The hard work isn't in the RTL," Lanza said. "It's getting the finished chip to work and to yield. There's no value over time in delivering RTL. But if you can deliver blocks that work — mindlessly work when you drop them into a design — and can make money at it, that's a business." Added Lanza: "Block-level design is inevitable." Both ARM's Goudge and Artisan's Templeton emphasized the amount of time and energy that went into documentation and support compared to design. "Ten to 20 percent of our time goes into development, Templeton said. "At least half our time goes into the delivery package that goes with the design." The panel discourage interest in digital IP vendors, but suggested that IP was, in effect, merging with the EDA world to become another part of the process of getting from requirements to yield. | 
