| PARIS — Philips Semiconductors has achieved what it claims is "right-first-time" silicon at its 90-nm CMOS production lines in France and Taiwan. The chips were fabricated at the Crolles2 wafer fab in Crolles, France, and at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). One of the world's first system-on-chips fabricated in the low-leakage 90-nm CMOS process in Crolles and Taiwan arrived "in time, on schedule and first time right," requiring "no re-spinning," said Jan-Marc Luchies, 90-nm CMOS program manager at Philips Semiconductors. The delivery allowef Philips to meet its chip design schedule right up to tapeout, according to the company. The 90-nm chip, which integrates an ARM processor core with SRAM, ROM and analog signal circuitry designed for a wireless application, represents commercially-targeted lead silicon, according to Philips. Luchies declined to comment on the current yield rate on the 90-nm CMOS low power process, but said that it's already good enough for sampling by selected customers. Volume production is slated for later this year. The low-leakage 90-nm CMOS process was developed by Philips and Crolles2 Alliance partners Motorola and STMicroelectronics. The new process is designed to give designers the option of a thicker gate oxide layer to control leakage currents. OEMs would benefit from the smaller chip size, while meeting crucial power consumption requirements, according to Philips. The CMOS090LP process achieves typical power savings of 75 percent compared to a 0.18-micron CMOS implementation. In terms of the silicon area occupied by digital circuitry, it offers up to a four-fold reduction, the company said. Philips taped out its first 90-nm silicon in December 2003, both in Crolles2 and TSMC. Since then, the company has completed several verification and check-off steps, including testing the booted chip in applications. Philips reported consistent performance between devices produced at the Crolles2 and TSMC fabs, said Luchies, claiming that "the early work done by the Crolles2 partners and TSMC in aligning the processes at the two fabs, both in terms of design rules and electrical parameters, has really paid off." When dealing with advanced processes, several things could go wrong during chip fabrication. Luchies said errors could be introduced through: mistakes in translating the spec into a net list; special I/Os between blocks could be fairly sensitive; a new fab line could have low yields; or a mismatch between models and silicon. In order to prevent mistakes, "we had to have separate teams dealing with each problem, and we had to coordinate all of their efforts," said Luchies. While separate 90-nm CMOS chip production lines are available in Crolles2, Philips, thus far, has focused on using the low power CMOS090 process. Philips also claimed the 90-nm project places it squarely in line with the International Technology Roadmap for Semiconductors. | 
