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Tensilica's New Xtensa LX Processor Earns Top BDTIsimMark2000 ScoreUpdate: Cadence Completes Acquisition of Tensilica (Apr 24, 2013) Offers Highest Signal Processing Speed of Any Licensable DSP Core or CPU Core Benchmarked to Date SANTA CLARA, Calif.– May 18, 2004 – Tensilica, Inc. today announced that it’s new Xtensa LX configurable processor core has achieved the highest score recorded to date for a licensable processor core on the BDTI Benchmarks by Berkeley Design Technology, Inc. (BDTI). The Xtensa LX BDTIsimMark2000 score of 6150 at 370 MHz is 70% faster than the score for the next-fastest licensable core benchmarked by BDTI, the CEVA-X1620.* For this benchmark, Tensilica created a unique, optimized processor configuration. Tensilica’s engineers used the Xtensa Processor Generator, selecting the check-box options that fit the benchmark. Then Tensilica’s engineers added 12 custom instructions using the TIE (Tensilica Instruction Extension) methodology to further accelerate performance hot spots in the algorithms. The configuration chosen for the BDTI Benchmarks™ is approximately 250K gates, occupies 4.4 mm2 and is projected to achieve a robust 370 MHz clock rate under worst case operating conditions in a commercially available 130 nm process from a leading wafer foundry. Tensilica reports that this high-performance DSP core minimizes power requirements, dissipating a mere 0.53 mW/MHz in dynamic (switching) power under typical operating conditions – producing a total power dissipation (dynamic plus leakage power) of only 200 mW at a 370 MHz operating speed.** Vectra LX DSP Engine About Tensilica * The BDTIsimMark2000™ provides a summary measure of DSP speed. For more information and scores see www.BDTI.com. Scores © 2004 BDTI. The Xtensa LX score assumes use of 12 custom TIE instructions that expand the area of the core by 16%. Licensees may require greater or lesser degrees of customization. The scores for all other cores assume that no coprocessors or other customizations were used. The scores for the Xtensa LX and all other cores are for worst case operating conditions in a commercially available 130 nm process. Contact info@BDTI.com for more information. ** The Xtensa LX configuration tested consumes a static leakage power of 5.5 mW plus dynamic switching power of 0.53 mW/MHz on a representative computational benchmark kernel under typical operating conditions (130 nm high-performance process – nominal process case, operating voltage 1.2V). # # # Editors’ Notes:
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