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LSI Logic Demonstrates 12 Gbit/S Serial Interface Circuitry in 90 Nanometer Process Technology
MILPITAS, Calif., June 14, 2004 -- LSI Logic Corporation (NYSE: LSI) today announced it has tested and validated 12 Gbit/s high-speed serial interface circuits in its G90TM 90-nanometer process technology. LSI Logics G90-based 12 Gbit/s interface technology enables serializer/deserializer (SerDes) cores with quadruple the bandwidth of existing backplanes and double the speed of planned 6 Gbit/s backplane upgrades. This industry-leading solution is designed to meet the requirements of the emerging Optical Internetworking Forum (OIF) CEI 11 LR (Long Reach) standard and provides a leap in performance for storage systems, networking, and telecommunications applications. With our demonstrated 12 Gbit/s serial interface technology, LSI Logic provides an easy path to increase system bandwidth so that our leading ASIC and RapidChipTM Platform ASIC customers can differentiate their high-speed datacom, telecom, and storage systems designs, said Jean Bou-Farhat, vice president, CoreWare, LSI Logic. We continue to push the leading edge of technology in order to meet customers requirements for time-to-market, performance, reliability and flexibility. In developing 12 Gbit/s serial interface technology, LSI Logic leveraged its extensive experience in high speed SerDes cores which support a range of applications from 155 Mbit/s SONET traffic to 6.4 Gbit/s backplane links. To achieve these breakthroughs with high-speed SerDes technology in 90 nanometer nodes, the companys high speed mixed signal engineers and packaging engineers worked closely together to provide a system solution with robust signal integrity, a necessary requirement for today's high-speed interfaces. About CoreWare About LSI Logic Corporation
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