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Sonics to deliver complete DRAM scheduler and controller subsystem IP for advanced digital ultimedia SoCs
Denali DataBahn™ now available from Sonics, Inc. with MemMax™ Memory Scheduler
Mountain View, Calif. — June 22, 2004 — Sonics, Inc., a leading provider of SOC (system-on-chip) architectures and SMART Interconnect IP products, and Denali Software, Inc., a leading provider of IP and EDA (Electronic Design Automation) products used to develop advanced memory sub-systems, today announced an agreement that gives Sonics the right to market the Denali Databahn memory controller optimized for interoperability with the Sonics MemMax Memory Scheduler. Sonics will provide a complete on-chip DRAM access scheduler and controller solution that will greatly speed and simplify development and debug of complex digital multimedia SOCs that need to optimize memory efficiency and throughput while minimizing system cost. Applications such as set-top-box and digital TV require high performance data throughput to and from off-chip memory but must maintain low system costs by implementing a unified memory architecture. An integrated memory controller and memory scheduler subsystem is essential to achieve those goals. Previously, SOC design teams were required either to build their own controller and scheduler, or acquire one or both blocks from third-party vendors and then attempt to tightly integrate the two timing sensitive IP blocks. With this new agreement, design teams can simply drop in the complete memory subsystem solution from Sonics and then configure the MemMax™ Memory Scheduler to reach required performance levels. “This agreement gives Sonics the ability to provide their customers a valuable advantage,” said Denali CEO and co-founder Sanjay Srivastava. “Instead of spending time in design, integration and verification tasks, Sonics’ customers now gain the advantage of a pre-verified and complete IP block that provides the maximum memory throughput to off-chip DRAM. Since DRAM can easily be the largest contributor to overall silicon expense, and thus system cost, this is a non-trivial and extremely important task. Sonics now make this much easier for their users.” “Our customers gain competitive advantage by simplifying SOC design and reducing risk, while gaining optimized performance,” said Grant Pierce, president and CEO of Sonics. “Denali has established Databahn as the leading memory controller and we are please to be able to team with them to provide leading edge SOC solutions at the SOC architecture stage. By integrating the market leading memory controller with our high performance memory scheduling IP we provide our users with yet another time-to-market advantage.” “Some of our leading OEM customers have already integrated Denali memory controllers with our MemMax and SiliconBackplane™ SMART Interconnect IP,” points out James Colgan, director of marketing at Sonics. “This new DRAM subsystem IP responds to our digital multimedia customers’ requirements for optimized performance and lower development risk.” “This integrated solution will help our customers meet the demanding performance goals of their multimedia SOCs within the tight market deadlines of the consumer multimedia market,” said Richard Tobias, vice president of the ASIC and Foundry Business Unit at Toshiba America Electronic Components, Inc. “This will save them time and eliminate the need for their multimedia SoC design teams to integrate these two essential components.” Memory systems are now the primary bottleneck to the flow of data in digital multimedia system-on-chip designs. Increasing clock speeds, new memory architectures, vendor-specific memory features and timing, and high-speed I/O effects are just some of the critical issues that must be addressed when designing a DRAM memory system. Denali’s Databahn cores provide a highly configurable, OCP compliant solution that promotes design re-use without re-work. Denali’s Databahn memory controller IP provides a flexible, comprehensive memory controller for a wide variety of new and emerging memory technologies including DDR, DDRII, and QDR for SDRAM, SRAM and RLDRAM applications operating up to 1.0Gbps. Sonics’ MemMax™ Memory Scheduler IP optimizes memory access to off-chip memory resources and improves DRAM utilization while reducing SOC die size. About Denali Software, Inc. About Sonics, Inc. SiliconBackplane, Sonics3220, SonicsStudio and MemMax are trademarks of Sonics, Inc. Denali, the Denali logo, Databahn, eMemory, MMAV, and PureSpec are trademarks of Denali Software, Inc.
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