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Synopsys' New PCI Express PHY IP Enables Lower Cost ICsDesignWare PCI Express PHY Area 50% Smaller than Competing Solutions MOUNTAIN VIEW, Calif., July 19, 2004 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in semiconductor design software, today announced the availability of its DesignWare® PCI Express™ Physical (PHY) layer intellectual property (IP), which rounds out a complete PCI Express Endpoint IP solution. Based on Synopsys' silicon-proven 6.25 Gbps backplane and high-speed SERDES (serializer-deserializer) technology, the DesignWare PCI Express PHY is optimized to be half the size, with twice the sensitivity and twice the jitter margin as competing solutions. These characteristics enable higher yield, better interoperability, lower field returns and ease-of-use in end applications. By combining the new PHY with its industry-leading PCI Express digital controller core and verification IP, Synopsys is offering designers a low-risk, integrated digital and mixed-signal IP solution for PCI Express applications. As high-volume products are beginning to require PCI Express functionality, designers are looking to embed both the digital core and mixed-signal PHY in their SoCs to reduce cost. Examples of PCI Express applications include high-speed graphics, video-enabled peripherals, along with other hardware connecting to PCs using Intel's recently released Grantsdale chip set. "With the introduction of our PCI Express PHY, designers can lower risk and shorten their design time by acquiring the complete PCI Express mixed-signal, digital and verification IP solution from a single supplier," said Guri Stark, vice president of Marketing, Synopsys' Solutions Group. "A very small die size, along with performance margin will enable both first-time and experienced high-speed SERDES designers to more cost effectively achieve high-volume production." Pricing and Availability About DesignWare IP For more information on DesignWare IP, visit: www.designware.com or call 1-877-4BEST-IP. About Synopsys
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