| Santa Cruz, Calif. — Seeking to provide an easy way to get software into silicon, the engineers and entrepreneurs who launched startup Poseidon Design Systems Inc. are revealing plans to offer electronic system-level (ESL) design tools that generate hardware accelerators for mathematically intensive software functions. Launched in Bangalore, India, in 2000, Poseidon is now chartered as a U.S. company based in Atlanta, although most of its 45 employees remain in India. By focusing on accelerating processor-based designs, the company's executives want to carve out a distinctive niche in the increasingly crowded ESL marketplace. Poseidon (www.poseidon-systems.com) is preparing a tool called Triton Tuner, which provides profiling and performance analysis, and Triton Builder, which offers hardware/software partitioning and generates RTL code for hardware accelerators. The tools are aimed at FPGAs, structured ASICs and system-on-chip designs and, thus far, have targeted wireless, video, multimedia and networking applications, said Farzad Zarrinfar, vice president of worldwide sales and marketing. "I think we have a pervasive opportunity in lots of applications," Zarrinfar said. "The convergence of multimedia, consumer, video and audio applications offers a tremendous opportunity with mathematically intensive functions. It's a great application for our technology, which can offload the CPU, optimize code and put it in an acceleration engine." Poseidon was co-founded by Ravi Janak, who serves as president and CEO; Suhas Hiwale, managing director of Indian operations; and Sarang Shelke, director of engineering for Indian operations. Janak's background is in software development and IT, while the other two founders have backgrounds in microprocessor development, Zarrinfar said. Recent additions to Poseidon's staff include Zarrinfar, who was previously vice president of worldwide sales at ARC International, and Bill Salefski, vice president of engineering, who was previously a vice president at Chameleon Systems Inc. and whose background also includes development work at Cadence Design Systems Inc. and Synopsys Inc. The company is currently raising about $10 million in venture capital, Zarrinfar said. Beta tests
Zarrinfar said that the company has several beta customers among top semiconductor companies but is not ready to release any names. The company expects production shipments of its Triton products during the fourth quarter. A large number of ESL startups have come to light within the past year, making differentiation a key challenge. But Poseidon has several "unique angles," said Zarrinfar. One is the company's acceleration engine, which, he said, uses a direct memory access (DMA)-based architecture to provide high performance, throughput and bandwidth. Another advantage, Zarrinfar said, is Triton's ability to provide a total package with its RTL code, including testbenches, drivers and modified C applications code. A third is the integration of accelerator generation with transaction-level verification. Poseidon is not the only company that claims to offload processors and accelerate mathematically intensive algorithms. But other companies in this area, said Salefski, tend to use VLIW hardware, which can't be deeply pipelined and may be difficult to implement on FPGAs. "We create a pipelined data compute engine instead, and we use DMA and local memories to feed data to it," Salefski said. "It's a nice clean way of putting acceleration into a design. You don't have updates to the compute core and you're not changing the rest of the system design." In essence, the Triton Builder generates a hardware accelerator that's a parameterized version of Poseidon's DMA based architecture. "In that sense, we have an IP [intellectual-property] library, but we're not positioning ourselves as an IP company," Salefski said. Triton Tuner takes in ANSI C applications, along with SystemC models for processors, buses and peripherals. It builds a simulation model and executes applications code on that model. It optimizes the memory hierarchy, tunes software algorithms, identifies "hot spots" in algorithms and identifies bottlenecks. Far from just giving an instruction count, Tuner tells users where cycles are going and which line of source code caused a pipeline stall or a cache miss, Salefski said. "What separates this from other SystemC tools is that it's really built for the systems and software engineer," he said. Triton Builder takes in applications code, an architectural description, and a processor and memory map. It analyzes code to identify portions that would benefit from hardware acceleration. Once the user decides which loops or instructions should be moved into hardware, it generates the RTL, along with the testbench and driver. Builder supports processors including ARM, Microblaze, PowerPC, Xilinx Spartan and Xilinx Virtex II/Pro. The quality question
After using Builder, users can return to Tuner to run transaction-level co-simulation and performance verification. One question that always emerges with automated RTL tools is quality of results compared with traditional methods. "We haven't done rigorous benchmarks, but I would say it's very close to what a good RTL systems designer would be able to do," Salefski said. He noted that the underlying acceleration architecture is based on hand-coded RTL, with the ability to do some parameterization. Tuner and Builder may be purchased separately or as a suite. Prices start at $30,000 for Tuner and $70,000 for Builder for one-year, time-based licenses. | 
