Aldec Announces the Industry's First Incremental Prototyping™ Methodology
Munich Germany (DATE Conference), March 13, 2001 -- The HES™ (Hardware Embedded SimulationTM) Business Unit of Aldec, Inc. announced today the industry's first RTL simulation acceleration platform incorporating Incremental Prototyping™ (IP) methodology for multi-million gate SoC design verification
Project Risk Reduction
Classical design flows using RTL simulation software exhibit exponentially increasing simulation times as designs grow to multi-million gate sizes. Large design sizes require hardware acceleration technology, but risk management resists the addition of new EDA tools to the established design flow as being too risky. Aldec's hardware accelerator, HES, along with Incremental Prototyping ™ technology provides verification accelerations on the order of 10-1000 times. More importantly the MTI®, Cadence®, and Synopsys® simulator users do not need to change their design flow or go through a learning curve to apply HES speed automatically to their design simulations.
Design Verification Targeted
SoC level designs commonly require multiple simulation runs as designs are first debugged and later optimized and verified to meet demanding design requirements. For small designs, the behavioral verification runs only hours, but most of today's designs are huge and require days and even weeks of simulation time. For this reason, SoC-sized designs have become practically impossible to verify without resorting to complex, time consuming specialized techniques such as hardware emulation. Additionally, since typical projects designate 45% to 55% of their scheduled time to verification the verification requirement drive project costs.
The Incremental Prototyping Platform
Aldec's HES Business Unit has developed a simplified, reliable and inexpensive design verification acceleration technology. This technology is based on Aldec's incremental design verification tools Active-HDL™ and Riviera™. The HES Design Verification Manager (DVM) eases implementation of Incremental Prototyping Technology (IPT) on current and new designs. As a result of HES speed and IPT, productivity costs drop by 40% or more.
The Incremental Prototyping Technology enables the designer to verify and optimize his or her design in manageable, smaller sized blocks according to project schedules. Each block is simulated in software by the HES Design Verification Manager before being "pushed" into the HES hardware. The HES resident blocks remain "connected" with HDL blocks by the Design Verification Manager in software. Each newly tested HDL block is being "pushed" into the HES hardware. At the end, most design blocks reside in the HES hardware and verification is performed in seconds instead of hours. The Incremental Prototyping process accelerates design development and implementation of the design requirements. Since testing requires only seconds, this allows designers to greatly increase the test bench coverage without incurring a major time penalty. This leads to enhanced quality of the design without traditional time penalties.
Simulators Supported
Users of Mentor and Cadence simulators can now achieve verification accelerations through FLI and PLI industry standard interfaces. The HES DVM is based on Mentor's proprietary design tools for Windows. The SUN-compatible HES accelerator speeds operation of Cadence and Mentor Graphics simulators on the order of 10-1000 times. Aldec's Active-HDL users already enjoy similar verification speed improvements with HES.
About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux, and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. http://www.aldec.com.
Active-HDL, Hardware Embedded Simulation, and Incremental Prototyping are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners
info@aldec.com for additional information on Aldec and the Active-HDL or Active-CAD product lines.
Copyright © 2001 Aldec, Inc Previous Page
