| SANTA CLARA, Calif. — System-level design has arrived, said Synopsys CTO and general manager Raul Camposano, in a keynote speech at an industry conference here Wednesday (Sept. 29). "System-level design is not the next big thing," said Camposano. "It has already happened and it is here." Camposano noted that as Moore's Law charges ahead, and design complexity and gate counts continue to increase, a growing productivity gap is forcing EDA companies to constantly create faster, higher-capacity tools to help customers design with the latest silicon. "One of the answers to raise productivity has been to raise the level of abstraction," said Camposano. "Instead of designing in transistors and gates, we should be designing systems." Camposano said moving to new levels of abstraction and designing systems hasn't proven a simple task, noting that there are multiple types of systems in every application area, each with unique requirements. This complicates the task of creating a single tool that will effectively address those multiple systems areas, he said. Complicating matters is the fact that as designs become more complex, new issues arise at the bank end of the process. Camposano noted that timing, signal integrity, power consumption, design for test and design for yield are all growing concerns with each drop in process geometry. Camposano noted that the EDA industry is addressing the problem of abstraction with ESL tools while IP companies are addressing system diversity by offering cores and platforms — ever larger predesigned pieces of a system on a chip. Camposano noted that while ESL design tools like synthesis are still maturing, ESL verification tools are in common use today. Still, Camposano estimated that ESL is currently a $100 million market, a small percentage of the $3.4 billion EDA market. Meanwhile, the IP market has grown into a $1 billion industry, making the combined IP and ESL markets a viable $1.1 billion system level design market. | 
