eASIC Ranked #1 Logic & Programmable Logic - Ultimate Product in a Survey of over 1,300 Engineers

In a study held by EE Times and eeProductCenter, Structured eASIC was ranked #1 on both “technical significance” and “usability”

San Jose, California, October 7, 2004 -- eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced that its Structured eASIC was ranked the #1 Ultimate Product in the Logic & Programmable Logic category of a study held by EE Times and eeProductCenter, surveying over 1,300 engineers, in order to allow sharing their experience with peers. The results of the survey were published by EE Times quarterly supplement called Ultimate Products. eASIC was ranked #1 in both criteria of “technical significance” and “usability”.

EE Times and eeProductCenter expert editors selected 10 of the most significant products introduced during the quarter, in each of seven categories, and then, using an electronic balloting mechanism, they submitted these products with the accompanying editorial reviews to selected, qualified readers of EE Times and eeProductCenter. The readers rated these products by two parameters: “technical significance” and “likelihood of use.”

“Innovations, such as eASIC’s, that help get products to market quickly are always greatly valued by engineers,” said Marty Gold, executive editor, eeProductCenter.

“We are very excited that our Structured eASIC was selected by engineers as the Ultimate Product in the Logic & Programmable Logic category,” said Zvi Or-Bach, Founder and CEO of eASIC. “Our innovative technology creates a paradigm shift in ASIC architecture and our NRE-free offerings are aimed at removing the barrier of entry for new designs. Together with our world class strategic partners, we are eager to serve the electronics engineering community by making ASIC easier, regaining the cost and time advantages we had in the old days”.

Structured eASIC Technology

eASIC has developed a unique Structured ASIC technology called Structured eASIC. The patented Structured eASIC architecture consists of an array of logic cells (eCells) with SRAM based LUTs (Look Up Tables) and flip-flops. eCells are inter-connected by a segmented wiring grid utilizing upper metal layers, which are customized per customer design with a single Via-mask. Logic programming of the eCell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and single custom Via-mask for customizing the routing. Moreover, single Via-customization is a perfect fit for an alternative lithography approach, namely the Direct-write eBeam. Using Direct-write eBeam completely eliminates the customization tooling cost, shortens time-to-market and adds manufacturing flexibility, allowing eASIC to provide the industry with a $0 NRE customized ASIC parts.
Furthermore, custom Via-masks can be later tooled for both the interconnect and the LUT contents to create a low-cost, “hard-wired” version for large volumes of the customer's design, without charging NRE.

Structured eASIC Product

Structured eASIC array, powered by eASIC’s technology, is aimed at drastically cutting development cost and turnaround time of ASIC designs. The first Structured eASIC product family has 4 members, raging from 600K to 3M gates, featuring embedded memory from 0.4M to 1.6M bits, programmable I/Os, PLLs and embedded microprocessor (8051). Supporting standard CAE tools or tailored Magma design flow, this product family is scheduled for release in Q1 2005.

About eASIC

eASIC® has developed a breakthrough Structured ASIC technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. eASIC’s technology enables rapid and low-cost ASIC and System-on-Chip designs by its innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.

eASIC Corporation is a privately held company, Venture Capital backed by Kleiner Perkins Caufield and Byers. Headquartered in San-Jose, California, eASIC was founded in 1999 by Zvi Or-Bach, the founder of Chip Express who is viewed by many as the “father of Structured ASIC technology”.
www.eASIC.com

Link to EE Times’ Ultimate Products Supplement

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