Adaptive Silicon Inc. (ASi) rolling out programmable core that reduces SoC costs

ASi rolling out programmable core that reduces SoC costs

ASi rolling out programmable core that reduces SoC costs
By Crista Souza, EBN
March 8, 2001 (2:41 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010308S0063

Adaptive Silicon Inc. today will unveil its long-awaited Programmable Logic Core, a block of intellectual property intended to reduce system-on-a-chip (SoC) engineering costs and make the chips more versatile.

Originally conceived as a way to speed market entry and reduce risk when working with evolving standards, ASi now says customers are most interested in constructing entire families of products from a single die-avoiding the rising cost of masks, prototype silicon, and parallel design efforts.

"With everyone we're talking to, this is the big driver," said Ralph Zak, vice president of marketing at ASi, Los Gatos, Calif.

Known as MSA 2500, the Programmable Logic Core (PLC) technology is available as a module in LSI Logic Corp.'s 0.18-micron G12 process. Test chips will be qualified on Taiwan Semiconductor Manufacturing Co. Ltd.'s 0.18-micron process in the second quarter.

LSI Logic is an investor in ASi, and the first PLC license e. The Milpitas, Calif., SoC manufacturer anticipates that within 10 years, it will derive 30% to 40% of its revenue from programmable products, said Ronnie Vasishta, director of ASIC marketing, speaking at a recent industry conference.

"We see the next, logical extension of SoC as embedded programmability for several reasons: one is the ability to adapt custom circuitry to more applications; another is time-to-market," Vasishta said. "Programmability adds flexibility for hardware verification in parallel with software development. That hasn't been available up to now for an SoC."

MSA 2500 cores use a Multi-Scale Array architecture consisting of 64-bit arithmetic logic units, equivalent to 1,500 gates. These blocks can be tiled in different patterns, depending on the I/O's density and word depth, in clusters of up to 25,000 gates, Zak said. Multiple clusters can be accommodated on one chip.

Hierarchical routing provides enough resources to handle complex or data-path-oriented designs, according t o ASi. Built-in self test and an Application Circuit Interface scan chain allow independent and concurrent testing of both core and ASIC.

The core connects to the rest of the chip via a configurable block containing bus interfaces such as the AMBA Advanced High Performance Bus.

ASi is also shipping its Millennium PLC software, which is designed to fit into a standard ASIC design flow. It incorporates synthesis libraries, a technology mapper, timing-driven placement, routing algorithms, timing closure tools, and a programming byte-stream generator.

MSA 2500 design licenses start at $300,000 per design. Manufacturing royalties run an average of 2 to 5 cents per block. Software seats are $50,000 per year.