IP licensees expand config core options

Including the deals announced last week with Broadcom Corp. and TTPCom Ltd., six year-old ARC now has nearly 100 licensees, which it said have produced some 100 million processors this year alone. "Industry leaders have begun recognizing that configurability has value," said Carl Schlachte, president and chief executive officer of ARC International (Cambridge, U.K.).

Broadcom (Irvine, Calif.), a licensee of the ARM and MIPS cores, said it added ARC's full range of configurable microprocessors and tools to expand its CPU options. "As we have many requirements, [additional cores] help us use the best technology for each application," said Rich Nelson, vice president of marketing for the broadband communications group.

Traditionally, chip developers have adopted a single instruction set architecture and then leveraged that investment and accumulated experience across product lines and generations. Increasingly, however, chip companies and system OEMs are willing to license configurable cores such as those of ARC or Tensilica Inc., even if they have longstanding relationships in the ARM or MIPS camp.

The growing number of licensees for configurable processing cores illustrates a "coming of age for configurability," said Schlachte, an intellectual property industry veteran who took the helm at ARC earlier this year.

The TTPCom license deal marks the first use of ARC's configurable processor in a mobile-handset baseband processor. TTPCom (Cambridge, U.K.) has implemented ARC's cores in the CBEmacro, a 2.75G baseband engine currently available worldwide.

To broaden their OEM base, developers of configurable processors have had to offer benefits beyond what's available with traditional architectures. Developers of battery-powered consumer products appreciate the configurability offered by ARC's cores, claimed Derek Meyer, the company's vice president of marketing.

Implementations of ARM or MIPS fixed cores are defined by the architecture, Meyer said. Licensees of those cores can adjust such parameters as cache size and organization, but "unless granted special rights, they are forbidden to change any of the architecture. With ARC, you can add instructions to the instruction sets or remove them, take away registers or gates, and reduce blocks."

As cost, performance and power requirements grow more stringent for OEMs, the ability to make such fundamental configuration changes appeals to architects. "I see momentum building for configurable processor cores like Tensilica and ARC, particularly in consumer electronics applications," said Jeff Bier, general manager of Berkeley Design Technology Inc. (BDTI). The trend, he said, has "less to do with the host processor" than with the "engines used for heavyweight processing tasks, such as video compression," in next-generation consumer devices.

While ARC has focused on the control plane, Tensilica argues that configurable processors — often used in clusters — can also be seen as alternatives to hardwired engines in the data plane. Tensilica's most recent offering provided a way to move data directly into the execution pipeline and to slash the energy consumption related to instruction fetch, decode and execution, making a wisely configured Tensilica core more comparable in energy efficiency to hardwired approaches.

ARM Ltd. and MIPS Technologies are also trying to accommodate such multimedia processing needs by adding features. ARM added an instruction set for motion estimation, BDTI's Bier said. But general-purpose CPUs "can't go faster than or [be] as scalable as configurable cores," he said.

ARM acknowledged an increasing demand for flexibility, albeit with a caveat. "There is a real space for configurability," said David Rose, director of consumer entertainment at ARM, "but not for CPUs."

ARM offers a standard product on the control plane and its OptimoDE data engine technology for the data plane. Based on tools acquired from Adelante Technologies, OptimoDE provides licensable, configurable IP with an associated tool environment. "For those who want to go down deep and dirty, OptimoDE helps you develop a configurable VLIW-styled architecture" targeted at high-performance embedded signal processing applications, said Mike Muller, ARM's CTO.

BDTI's Bier called OptimoDE "a very relevant technology" for competing on ARC and Tensilica's turf. ARM signed Thomson as an OptimoDE licensee in November, but the technology thus far is growing slowly, Bier said.

Seeking gain without pain
The trend in consumer electronics is toward configuration, customization and differentiation, "but at low cost," said Paul O'Donovan, principal analyst of Consumer Electronics Research at Gartner Inc.'s Semiconductor Group. Compared with a classic custom ASIC, configurable cores can offer a flexible solution "with, hopefully, the benefits of lower silicon costs and fast time-to-market," he said.

Jim Tully, vice president and chief of research for Gartner Research, said he does not see "a big transition to configurable cores in the consumer space." But some of the growing number of consumer applications "are being captured by configurable architectures," he said.

The attraction of the configurable processor here is that it can be matched closely to specific application requirements. "This means a smaller processor core [in terms of silicon area] can be used," said Tully. "That can be important in high-volume applications."

Configurable cores also present challenges, primarily in verification and in maintenance and support for a new instruction set.

By configuring the instruction set, a licensee creates a problem in that new instructions, if they are to be truly effective, must be handcrafted into the licensee's code. The licensee thus is forced "into the processor design business, requiring a level of expertise and detailed knowledge of an algorithm and a processor," BDTI's Bier said.

Further, as a licensee configures a licensed core for a specific application, each reconfigured core becomes different, making it much harder and more complicated to move software originally developed for one configurable core to another. The bottom line is that "configurable cores become only applicable if one is designing a custom chip," Bier said. This tendency clashes with the much larger industry trend of SoC designers striving to do higher-level abstractions.

On the issue of verification, ARC and Tensilica assure customers that their processor configuration tools automatically generate a verification suite for new instructions that can't break existing RTL. But customers are still creating a new CPU core, which inevitably engenders a new verification problem. A prudent design team will still want to verify the whole core, with changes. That's a huge job, and an uncertain one.

The biggest drawback of configurable processors, Gartner's Tully said, is "in the tools." Fixed processors can provide compilers, debuggers and other tools optimized to a particular fixed architecture. "If customers are allowed to make changes to the processor, the tools need to be changed too. Vendors are going to have a tough time supporting tools [and processors] that are different for every user."

Retargetable compiler technology has existed for decades, so simply supporting a new instruction set is not a huge problem. Special, complex instructions can always be accommodated by encapsulating them in explicit function calls. But years of learning have gone into the optimizing compilers for established instruction set architectures, and that advantage cannot be shared with a new instruction set.

ARC and Tensilica are mindful of such pitfalls and are sensitive to the fact that not every OEM is stocked with experienced CPU architects. Both companies have created application-specific packages with preconfigured CPUs for particular tasks.

For example, rather than leave its core's configurability for multimedia processing entirely up to licensees, ARC recently launched the ARCsound Audio Subsystem. It consists of audio software, an ARC processor with custom audio extensions and a full suite of hardware and software development tools.

ARC is reportedly working on a similar subsystem for various video compression algorithms, likely for introduction next year. Schlachte, however, declined to comment on its schedule.

— Additional reporting by Ron Wilson