| GRENOBLE, France — A panel discussion on verification intellectual property, conducted without the usual pre-amble of positioning statements, found an audience of design engineers and EDA executives at the IP-SOC conference here. With just a brief introduction of the panelists — Wolfgang Ecker, principal verification engineer at Infineon Technologies AG, Laurent Ducousso of STMicroelectronics, Aleksander Randjic, of HDL Design House and Phil Dworsky, director of marketing for Synopsys' DesignWare IP — the moderator pitched right into the quizzing the panel about the necessity and completeness of VIP and contrasting it with DIP, or design intellectual property. Infineon's Ecker was adamant that VIP was necessary because it did not make sense to come up with the same interface to prove logic blocks time and time again. This view was endorsed by all the panelists. Dworsky's observed that more than 25 percent of Synopsys customers have more than six standard interfaces on their SoCs and developers want to achieve confidence that these are compliant to their respective specifications as quickly as possible. But his comment also highlighted that third-party VIP tends to focus on third-party standards-based DIP. "Processor models are probably best tested by the people who developed them," said Dworsky. Elsewhere the debate revolved about how a verification engineer could judge the quality of the VIP he is being offered, particular when such offerings have to be recreated across different tool flows and for different simulation environments and languages. "In design there are two languages VHDL and Verilog but there are many suppliers. But for Vera and E each has no second source," said Infineon's Ecker. "We have no QA for VIP we have to use the designs to check the VIP," lamented Ecker. "Code coverage is useless as a metric." Although Randjic and Dworksy argued that the process of checking out VIP is pretty much the same as when judging a DIP offering, involving asking about how many times a piece of VIP had been used in designs, the bug detection history, and so on, Dworsky added: "QUIP is not going to give you an answer but it is a great starting place for discussion." Ecker and ST's Ducousso ended that cycle of debate by suggesting that the best insurance is to draw up an agreed qualification process for the VIP developer and that makng the supplier follow good practice was the best protection for the VIP user. A further question from the floor asked about the prospects of analog and mixed-signal verification IP, and received the general answer that VIP is a digital thing, before Ecker admitted that Infineon has some internal work on formalizing the verification of analog IP. As to the future Randjic argued that verification technology would go where the design technology goes. So a layered verification approach that handles gates, RTL and the transaction level was required. "Specman from Verisity does address, or will address, all these layers." However, to a question from the floor on whether a layered approach could be made industry-wide and provide benefits, Randjic could see no need. Infineon's Ecker took a different position arguing that the incompleteness of verification methods remains a problem and that despite the many false starts formal methods and assertion checks provided a way forward. "There's a strong push behind formal methods. We can do sub-blocks. If we could do whole chips we would," said Ecker. | 
