Altera Updates Specifications for Stratix II FPGAs Reflecting Higher Performance and Lower Power

San Jose, Calif., January 31, 2005—As its Stratix^® II FPGA family moves into volume production, Altera Corporation (NASDAQ: ALTR) today released new specifications reflecting faster performance and lower power. With these enhanced specifications, the maximum operating frequencies of the Stratix II family’s DSP blocks, internal memories, and high-speed LVDS signaling have increased by up to 20 percent. In addition, Stratix II FPGAs consume 45 percent less static power than previously specified: as low as 0.18 Watts at 25oC for the EP2S15 device.

Stratix II devices are the industry’s fastest and biggest FPGAs, with 39 percent better performance on average and 82 percent more logic elements (LEs) than the closest competing device. The new specifications give Stratix II FPGAs an additional boost of performance for digital signal processing (DSP), memory, and I/O-intensive applications. Quartus^® II design software version 4.2 has been updated to enable customers to take advantage of these increases in performance, which include:

• DSP block: from 350 MHz to 420 MHz
• M-RAM block: from 350 MHz to 400 MHz
• M4K block: from 350 MHz to 400 MHz
• M512 block: from 370 MHz to 380 MHz
• LVDS: from 800 Mbps to 1040 Mbps
• Demonstrated RLDRAM II clock speed >440 MHz
  

“The Stratix II architecture has been designed to maximize performance while virtually eliminating in-rush power and minimizing total device power,” said David Greenfield, Altera’s senior director of product marketing for high-density FPGAs. “The stellar performance of Stratix II FPGAs provides a competitive advantage for customers designing high-end systems.”

New Specifications for Power Consumption

New specifications highlight lower power consumption of the Stratix II family. For the EP2S60ES device, for example, a surge current of 2A has been eliminated in the production devices, which now exhibit an ideal monotonic rise in power-up current. This is in addition to the 45 percent reduction in static power across the Stratix II family. Furthermore, the Stratix II FPGA total I/O pin capacitance (including silicon, substrate, and package) values range from 3.3 pF to 6.1 pF, which leads to lower total power consumption and is 50 percent lower than the measured values of the closest competitor’s I/O pin capacitance.

Power consumption has two major components, static and dynamic, with dynamic power being the dominant component in total device power. Since dynamic power is design-dependent, accurate power analysis tools are critical to understanding total power consumption. Altera’s PowerPlay power analysis tools found in Quartus II development software are the only tools that accurately estimate total device power for high-density 90-nm FPGAs across the full spectrum of operating conditions. Key capabilities of the power analysis tools include:

• Automatic model generation from Quartus II software
• Accurate modeling of temperature effects  
• Inclusion of heat sink and air flow settings  
• Utilization of full logic mapping, placement, and routing information  
• Generation of accurate toggle information from simulation vectors

For more information about the Stratix II family’s performance enhancements please visit: www.altera.com/products/devices/stratix2/features/performance/st2-perf_improvements.html.

For more information about the Stratix II family’s power solutions, please visit: www.altera.com/products/devices/stratix2/features/st2-power.html.

About Altera

Altera Corporation (NASDAQ: ALTR) is the world’s pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.

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