ESL Design State of the Union 2005

By Bill Murray

Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies, and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems.

These ESL design methodologies target the perennial embedded system design challenges of hardware/software (HW/SW) co-development – challenges that are particularly acute in systems that utilize architectures with multiple heterogeneous processors and that deploy sophisticated algorithms with high data throughput requirements. They deliver not only dramatic improvements in productivity and time to market, but also – crucially – enable the design team to identify and solve functionality and performance problems early in the design flow – problems that in traditional embedded system design are all too often detected only at system bring-up.

ESL HW/SW co-development methodologies leverage high-level modeling and simulation techniques to create an ‘executable specification’ of the design. Comprehensive, up-front design space exploration using deterministic functionality and performance analysis capabilities speeds and optimizes HW/SW partitioning decisions and hardware architecture development, while the resultant system architecture models enable embedded software development, and fast HW/SW co-verification and co-debug months before hardware availability; hardware design, rapid hardware IP integration, re-use and derivative design; and a hardware architecture-to-implementation verification strategy that encompasses testbenches, emulation, hardware-enabled acceleration, formal and semi-formal methods.

ESL hardware design and verification methodologies leverage high level synthesis and configurable IP techniques to automate the development of programmable and non-programmable engines that execute faster than general purpose processors, and often with less power consumption. These methodologies deliver in days or weeks a design that requires engineer-years of effort using traditional design techniques. For instance, custom processors, coprocessors and (in some cases) their associated software development tools are generated automatically from a ‘golden’ source such as a language-based architectural description or the embedded software itself, while dedicated hardware engines are generated automatically from mathematical, graphical or language-based ‘golden’ reference algorithm descriptions, or from an embedded software implementation of the algorithm. The synthesizable RTL output of such methodologies flows seamlessly into the traditional RTL-down flows for SoC and/or system-on- FPGA implementations.

The language-based and embedded software-driven methodologies utilize industry standard languages – or proprietary derivations thereof – with which system hardware and software developers are familiar, namely C/C++ and SystemC, while the mathematical and graphical methodologies utilize approaches with which developers of domain-specific algorithms – particularly DSP – are often familiar.

ESL design and verification methodologies are essential to the fast-turn, optimal hardware/software codevelopment necessary to produce high performance, low power embedded systems of considerable architectural and algorithmic complexity. Not surprisingly, therefore, the ‘early adopters’ of ESL design were the developers of SoCs and software for mobile phones and other high volume, software-rich consumer appliances – mainstream products that have mainstreamed ESL design.

Bill Murray is an independent consultant to the EDA, Embedded System, Semiconductor and Wireless industries.