|
||||||||||
MIPS Architecture Selected by Infineon as Standard for its VoIP SolutionsMIPS32® 24Kc™ and M4K™Processors Form the Basis for Development of Infineon’s Broadband ICs MOUNTAIN VIEW, CA, March 7, 2005 – MIPS Technologies, Inc. (NASDAQ: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer and business applications, today announced that Infineon Technologies AG (FSE/NYSE: IFX), a world leader in voice access ICs, has standardized upon the MIPS32 ® 24Kc ™ and the MIPS32 M4K ™ processor cores for future development of its growing VoIP business. A MIPS licensee since 2000, Infineon is one of the world’s leading broadband access IC providers that is shipping numerous MIPS-Based ™ broadband CPE products including advanced xDSL modems, routers, home gateways and VoIP telephony. “For several years now we have been using the MIPS architecture to develop innovative high performance and quality VoIP solutions including IP Phones, Analog Telephone Adapters (ATA) and VoIP-enabled Gateways at competitive costs,” said Ulrich Huewels, VP of System Engineering COM Access, Infineon Technologies AG. “Infineon continues working closely with MIPS Technologies to design improved and flexible communication solutions leveraging the proven capabilities of the MIPS architecture.” “Infineon’s choice to broaden our long-standing alliance underscores the growing success our customers are having in the CPE and communications markets,” said Cesar Martin-Perez, vice president of European operations at MIPS Technologies. “We are delighted to have Infineon join the growing list of MIPS32 24K ® core customers. The 24K core licensing growth is faster than any product from MIPS Technologies and is driven by its competitive advantages – both greater performance and smaller die area. We look forward to supporting their efforts to penetrate their target markets with their MIPS-Based product line.” About the MIPS32 24K Core Family The MIPS32 M4K core gives designers more performance and greater flexibility to achieve higher system throughput while controlling silicon cost. The flexibility and re-programmability enables upgrades in software as protocol specifications or market requirements evolve. Other features include bit field instructions for easier handling of packet information, support for vectored interrupts to decrease interrupt latency, and multiple register sets for faster context switching. About MIPS Technologies
|
Home | Feedback | Register | Site Map |
All material on this site Copyright © 2017 Design And Reuse S.A. All rights reserved. |